SY89825UHY Micrel Inc, SY89825UHY Datasheet - Page 5

• Manufacturer Part Number: SY89825UHY
• Description: IC CLK DRVR/XLATOR LVDS 64-TQFP
• Manufacturer: Micrel Inc
• Series: Precision Edge®r
• Type: Fanout Buffer (Distribution), Multiplexer , Translatorr

Specifications of SY89825UHY

• Number Of Circuits: 1
• Ratio - Input:output: 2:22
• Differential - Input:output: Yes/Yes
• Input: LVDS, LVPECL
• Output: LVPECL
• Frequency - Max: 2GHz
• Voltage - Supply: 2.37 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP Exposed Pad, 64-eTQFP, 64-HTQFP, 64-VQFP
• Frequency-max: 2GHz
• Number Of Clock Inputs: 2
• Mode Of Operation: Differential
• Output Frequency: 2000MHz
• Output Logic Level: LVPECL
• Operating Supply Voltage (min): 2.37V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Package Type: TQFP EP
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Signal Type: LVDS/LVPECL
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 576-2566; SY89825UHY

Micrel, Inc.
V
Notes:
1. Outputs loaded with 50
2. f
3. Differential propagation delay is defined as the delay from the crossing point of the differential input signals to the crossing point of the differential
4. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device operating at the same
5. The part-to-part skew is defined as the absolute worst case difference between any two delay paths on any two devices operating at the same
6. Set-up and hold time applies to synchronous applications that intend to enable/disable before the next clock cycle. For asynchronous applications,
7. Random jitter is measured using K28.7 pattern, measured at
8. Cycle-to-cycle definition: the variation of periods between adjacent cycles, Tn–Tn-1 where T is the time between rising edges of the output signal.
9. Total jitter definition: with an ideal clock input of frequency
M9999-011907
[e-mail] or [phone]
Symbol
f
t
t
t
t
t
t
t
t
t
CC
MAX
PHL
PLH
SKEW
S(OE)
H(OE)
JITTER
r
f
(switchover)
AC ELECTRICAL CHARACTERISTICS
output signals.
voltage and temperature.
voltage and temperature. Part-to-part skew is the total skew difference; pin-to-pin skew + part-to-part skew.
set-up and hold time does not apply. OE set-up time is defined with respect to the rising edge of the clock. OE HIGH to LOW transition ensures
outputs remain disabled during the next clock cycle. OE LOW to HIGH transition enables normal operation of the next input clock.
specified peak-to-peak jitter value.
MAX
= 2.37V to 3.6V, GND = 0V
is defined as the maximum toggle frequency measured. Measured with a 750mV input signal, all loading with 50 to V
Max Toggle Frequency
Propagation Delay
(Differential)
Within-Device Skew
Part-to-Part Skew
OE Set-Up Time
OE Hold Time
Random Jitter
Cycle-to-Cylce Jitter
Total Jitter
Output Rise/Fall Time
(20% – 80%)
Input Switchover
CLK_SEL-to-valid output
Parameter
(9)
to V
(3)
(6)
(7)
CC
(6)
(5)
– 2V. Airflow
LVPECL IN
(4)
(8)
LVDS IN
(2)
300lfpm.
0.600
0.800
Min.
300
1.0
0.5
—
—
—
—
—
—
2
T
A
(1)
f
= –40 C
MAX
Typ.
100
f
—
—
—
—
—
—
—
—
—
—
—
MAX
, no more than one output edge in 10
.
Max.
5
200
600
1.2
1.4
1.2
35
10
—
—
—
1
1
0.600
0.800
Min.
300
1.0
0.5
—
—
—
—
—
—
2
T
A
= +25 C
0.900
Typ.
100
450
1.1
20
—
—
—
—
—
—
—
Max.
20
200
600
1.2
1.4
1.2
—
35
—
—
10
1
1
output edges will d eviate by more than the
0.600
0.800
Min.
300
1.0
0.5
—
—
—
—
—
—
2
T
A
= +85 C
Typ.
100
CC
—
—
—
—
—
—
—
—
—
—
—
–2V.
Precision Edge
Max.
200
600
1.2
1.4
1.2
35
10
—
—
—
1
1
SY89825U
ps
ps
ps
Unit
GHz
(RMS)
(RMS)
ns
ps
ps
ns
ns
ps
ns
(PP)
®