SY898531LTZ Micrel Inc, SY898531LTZ Datasheet - Page 3

• Manufacturer Part Number: SY898531LTZ
• Description: IC BUFFER 1:9 LVPECL 32TQFP
• Manufacturer: Micrel Inc
• Series: Precision Edge®r
• Type: Fanout Buffer (Distribution), Multiplexerr

Specifications of SY898531LTZ

• Number Of Circuits: 1
• Ratio - Input:output: 2:9
• Differential - Input:output: Yes/Yes
• Input: HCSL, LVDS, LVHSTL, LVPECL, SSTL
• Output: LVPECL
• Frequency - Max: 500MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-TQFP, 32-VQFP
• Frequency-max: 500MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 576-3709; SY898531LTZ

Micrel, Inc.
Pin Description
Truth Table
October 2009
9, 16, 17, 24,
Pin Number
CLK_EN
25, 32
30, 31
28, 29
26, 27
22, 23
20, 21
18, 19
14, 15
12, 13
10, 11
2, 3
5, 6
7
8
4
1
0
0
1
1
PCLK, /PCLK
CLK_SEL
CLK, /CLK
Pin Name
CLK_SEL
CLK_EN
Inputs
Q0, /Q0
Q1, /Q1
Q2, /Q2
Q3, /Q3
Q4, /Q4
Q5, /Q5
Q6, /Q6
Q7, /Q7
Q8, /Q8
V
V
V
0
1
0
1
CCO
CC
EE
Selected Source
PCLK, /PCLK
PCLK, /PCLK
Pin Function
Ground.
Single-Ended Input: This TTL/CMOS input disables and enables the Q0-Q8 outputs. It is
internally connected to a 50kΩ pull-up resistor and will default to a logic HIGH state if left
open. When disabled, Q goes LOW and /Q goes HIGH. Since CLK_EN is synchronous
with the input clock, the outputs will be enabled/disabled following a rising and a falling
edge of the input clock. V
Single-Ended Input: This single-ended TTL/CMOS-compatible input selects the input to
the multiplexer. Note that this input is internally connected to a 50kΩ pull-down resistor
and will default to logic LOW state if left open. V
Differential Input: This input pair is a differential signal input to the device. This input
accepts AC- or DC-coupled signals. CLK is internally connected to a 28kΩ pull-down
resistor and will default to a logic LOW state if left open while /CLK is connected to a
50kΩ pull-up resistor and will default to a logic HIGH state if left open. This input pair is
selected when CLK_SEL is set to logic LOW.
Differential Input: This input pair is a differential signal input to the device. This input
accepts AC- or DC-coupled signals. PCLK is internally connected to a 50kΩ pull-down
resistor and will default to a logic LOW state if left open while /PCLK is connected to a
50kΩ pull-up resistor and will default to a logic HIGH state if left open. This input pair is
selected when CLK_SEL is set to logic HIGH.
Positive Power Supply Pin: Bypass with 0.1µF||0.01µF low ESR capacitor as close to the
V
Output Positive Power Supply Pins: Bypass with 0.1µF||0.01µF low ESR capacitors as
close to the V
LVPECL Differential Output Pairs: Differential buffered output copies of the selected input
signal. The output swing is typically 800mV. Unused output pairs may be left floating with
no impact on jitter. These differential LVPECL outputs are a logic function of the CLK,
/CLK and PCLK, /PCLK, and CLK_SEL inputs. See “Truth Table” below.
CLK, /CLK
CLK, /CLK
CC
pin as possible.
CCO
pins as possible.
Disabled : LOW
Disabled : LOW
Q0 :Q8
PCLK
CLK
TH
4
= is approximately 1.5V.
Outputs
Disabled : HIGH
Disabled : HIGH
/Q0:/Q8
/PCLK
/CLK
TH
= is approximately 1.5V.
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SY898531L