SY89856UMG Micrel Inc, SY89856UMG Datasheet - Page 3

• Manufacturer Part Number: SY89856UMG
• Description: IC 2GHZ 1:6 LVPECL FANOUT 32-MLF
• Manufacturer: Micrel Inc
• Series: Precision Edge®r
• Type: Fanout Buffer (Distribution), Multiplexerr

Specifications of SY89856UMG

• Number Of Circuits: 1
• Ratio - Input:output: 2:6
• Differential - Input:output: Yes/Yes
• Input: CML, LVDS, PECL
• Output: LVPECL
• Frequency - Max: 3GHz
• Voltage - Supply: 2.375 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-MLF®, QFN
• Frequency-max: 3GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 576-2102-5; SY89856UMG

August 2007
Pin Description
LVPECL Output Interface Applications
Pin Number
9, 17, 24, 32
11, 16, 18,
23, 25, 30
29, 28
27, 26
22, 21
20, 19
15, 14
13, 12
5, 8
2, 6
3, 7
1,4
31
10
SEL
0
1
Exposed Pad
VREF-AC0
VREF-AC1
Pin Name
VT0, VT1
IN0, /IN0
IN1, /IN1
Q0, /Q0,
Q1, /Q1,
Q2, /Q2,
Q3, /Q3,
Q4, /Q4,
Q5, /Q5
GND,
VCC
SEL
NC
Pin Function
Differential Input: These input pairs are the differential signal inputs to the
device. These inputs accept AC- or DC-coupled signals as small as 100mV
(200mV
Note that these inputs will default to an indeterminate state if left open. Please
refer to the “Input Interface Applications” section for more details.
Input Termination Center-Tap: Each side of the differential input pair terminates
to a VT pin. The VT0 and VTI pins provide a center-tap to a termination network
for maximum interface flexibility. See “Input Interface Applications” section for
more details.
This single-ended TTL/CMOS-compatible input selects the inputs to the
multiplexer. Note that this input is internally connected to a 25kΩ pull-up resistor
and will default to logic HIGH state if left open. The MUX select switchover
function is asynchronous.
No connect.
Positive Power Supply: Bypass with 0.1µF//0.01µF low ESR capacitors as close
to VCC pins as possible.
Differential Outputs: These 100k (temperature compensated) LVPECL output
pairs are low skew copies of the selected input. Unused output pins may be left
floating. Please refer to the “LVPECL Output Interface Applications” for details.
Ground: Ground pins and exposed pad must be connected to the same ground
plane.
Reference Voltage: This output biases to V
inputs (IN, /IN). Connect VREF_AC directly to the VT pin. Bypass with 0.01µF
low ESR capacitor to V
sink/source current is ±1.5mA. Due to the limited drive capability use for input at
the same package only.
p-p
). Each pin of a pair internally terminates to a VT pin through 50Ω.
IN0 Input Selected
IN1 Input Selected
Output
3
CC
. See “Input Interface Applications” section. Maximum
[e-mail]
CC
–1.2V. It is used for AC-coupling
or [phone]
M9999-082907-C