SY89833LMG Micrel Inc, SY89833LMG Datasheet - Page 5

• Manufacturer Part Number: SY89833LMG
• Description: IC BUFFER/XLATOR 1:4 LVDS 16MLF
• Manufacturer: Micrel Inc
• Series: Precision Edge®r
• Type: Fanout Buffer (Distribution), Translatorr

Specifications of SY89833LMG

• Number Of Circuits: 1
• Ratio - Input:output: 1:4
• Differential - Input:output: Yes/Yes
• Input: CML, LVDS, LVPECL
• Output: LVDS
• Frequency - Max: 2GHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-MLF®, QFN
• Frequency-max: 2GHz
• Device Type: Differential Buffer
• Supply Current Max: 45mA
• Peak-to-peak Jitter Max: 200ps
• Signal Input Type: CMOS, TTL
• Output Level Type: LVDS
• Supply Voltage Range: 3V To 3.6V
• Number Of Outputs: 8
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 85C
• Propagation Delay Time: 0.6ns
• Operating Supply Voltage (min): 3V
• Mounting: Surface Mount
• Pin Count: 16
• Operating Supply Voltage (typ): 3.3V
• Package Type: MLF
• Input Frequency: 2GHz
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 576-1433

Micrel, Inc.
V
Symbol
f
t
t
t
t
t
t
Notes:
7.
8.
9.
10. Set-up and hold times apply to synchronous applications that intend to enable/disable before the next clock cycle. For asynchronous applications,
11. Random jitter is measured with a K28.7 pattern, measured at ≤f
12. Deterministic jitter is measured at 2.5Gbps with both K28.5 and 2
13. Cycle-to-cycle jitter definition: The variation period between adjacent cycles over a random sample of adjacent cycle pairs. t
14. Total jitter definition: with an ideal clock input frequency of ≤ f
August 2007
MAX
pd
SKEW
S
H
JITTER
r
, t
CC
AC ELECTRICAL CHARACTERISTICS
TIMING DIAGRAM
f
High-frequency AC parameters are guaranteed by design and characterization.
Within device skew is measured between two different outputs under identical input transitions.
Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and no skew at the edges at the respective
inputs.
set-up and hold times do not apply.
where T is the time between rising edges of the output signal.
than the specified peak-to-peak jitter value.
= +3.3V ±10%; R
Parameter
Maximum Frequency
Propagation Delay
Within-Device Skew
Part-to-Part Skew
Set-Up Time
Hold Time
Data
Clock
Output Rise/Fall Times
(20% to 80%)
Random Jitter (RJ)
Deterministic Jitter (DJ)
Cycle-to-Cycle Jitter
Total Jitter (TJ)
L
= 100Ω across the outputs; T
EN
/IN
IN
/Q
Q
V
IN
t
pd
EN to IN, /IN
EN to IN, /IN
V
t
S
CC
IN-to-Q
IN-to-Q
/2
A
Condition
V
V
V
Note 8
Note 9
Note 10
Note 10
Note 11
Note 12
Note 13
Note 14
At full output swing.
= –40°C to +85°C unless otherwise stated.
OUT
IN
IN
(7)
< 400mV
≥ 400mV
MAX
≥ 200mV
MAX
23
(device), no more than one output edge in 10
t
–1 PRBS pattern.
.
H
5
V
CC
/2
t
pd
[e-mail] or [phone]
Min
400
330
300
500
2.0
12
60
output edges will deviate by more
V
Typ
500
440
110
OUT
5
JITTER_CC
Precision Edge
Max
600
530
200
190
20
10
10
M9999-082407
1
1
= T
SY89833L
n
–T
ps
ps
Units
ps
ps
GHz
n+1
ps
ps
ps
ps
ps
ps
ps
RMS
RMS
PP
PP
,
®