SI5368C-C-GQR Silicon Laboratories Inc, SI5368C-C-GQR Datasheet - Page 61

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SI5368C-C-GQR

Manufacturer Part Number
SI5368C-C-GQR
Description
IC CLK MULTIPLIER ATTEN 100TQFP
Manufacturer
Silicon Laboratories Inc
Datasheet

Specifications of SI5368C-C-GQR

Input
*
Output
*
Frequency - Max
*
Voltage - Supply
*
Operating Temperature
*
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Frequency-max
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SI5368C-C-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Reset value = 0000 0010
Register 132.
Name
Type
Bit
Bit
7
6
5
4
3
2
Reserved
ALIGN_FLG
FOS4_FLG
FOS3_FLG
FOS2_FLG
FOS1_FLG
Reserved
Name
D7
R
ALIGN_
Reserved.
ALIGN_FLG.
Alignment Alarm Flag.
0: Normal operation.
1: Held version of ALIGN_INT. Generates active output interrupt if output interrupt pin is
enabled (INT_PIN=1) and if not masked by ALIGN_MSK bit. Flag cleared by writing
location to 0.
FOS4_FLG.
CLKIN_4 Frequency Offset Flag.
0: Normal operation.
1: Held version of FOS4_INT. Generates active output interrupt if output interrupt pin is
enabled (INT_PIN=1) and if not masked by FOS4_MSK bit. Flag cleared by writing
location to 0.
FOS3_FLG.
CLKIN_3 Frequency Offset Flag.
0: Normal operation.
1: Held version of FOS3_INT. Generates active output interrupt if output interrupt pin is
enabled (INT_PIN=1) and if not masked by FOS3_MSK bit. Flag cleared by writing
location to 0.
FOS2_FLG.
CLKIN_2 Frequency Offset Flag.
0: Normal operation.
1: Held version of FOS2_INT. Generates active output interrupt if output interrupt pin is
enabled (INT_PIN = 1) and if not masked by FOS2_MSK bit. Flag cleared by writing
location to 0.
FOS1_FLG.
CLKIN_1 Frequency Offset Flag.
0: Normal operation.
1: Held version of FOS1_INT. Generates active output interrupt if output interrupt pin is
enabled (INT_PIN = 1) and if not masked by FOS1_MSK bit. Flag cleared by writing
location to 0.
FLG
R/W
D6
FOS4_FLG FOS3_FLG FOS2_FLG FOS1_FLG
R/W
D5
Preliminary Rev. 0.41
R/W
D4
Function
R/W
D3
R/W
D2
LOL_FLG
R/W
D1
Si5368
ERR [8,8]
ALIGN_
D0
R
61

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