PI6CU877NFE Pericom Semiconductor, PI6CU877NFE Datasheet

PI6CU877NFE

Manufacturer Part Number

PI6CU877NFE

Description

IC PLL CLOCK DRIVER DDR2 52VFBGA

Manufacturer

Pericom Semiconductor

Type

PLL Clock Driverr

Datasheet

1.PI6CU877NFE.pdf (12 pages)

Specifications of PI6CU877NFE

Input

SSTL-18

Output

SSTL-18

Frequency - Max

270MHz

Voltage - Supply

1.7 V ~ 1.9 V

Operating Temperature

0°C ~ 70°C

Mounting Type

Surface Mount

Package / Case

52-VFBGA

Frequency-max

270MHz

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

BOSTOCK HK LIMITED

Part Number:

PI6CU877NFE

Manufacturer:

Pericom

Quantity:

10 000

Current page: 1 of 12
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Features

• PLL clock distribution optimized for DDR2-667/533/400

• Distributes one differential clock input pair to eleven differ-

• Differential Inputs (CLK, CLK) and (FBIN, FBIN)

• Input OE/OS: LVCMOS

• Differential Outputs (Y[0:9], Y[0:9] and (FBOUT, FBOUT)

• External feedback pins (FBIN, FBIN) are used to

• Operates at AV

• Packaging (Pb-free & Green):

• PI6CU877 for DDR2-533/400 applications

• PI6CUA877 for DDR2-667/533/400 applications

Pin Confi guration

SDRAM applications.

ential clock output pairs.

synchronize the outputs to the clock input.

and V

– 52-ball VFBGA (NF)

AGND

08-0298

DDQ

= 1.8V for differential output drivers

GND

DDQ

= 1.8V for core circuit and internal PLL,

GND

DDQ

GND

DDQ

GND

DDQ

OUT

Description

PI6CU877 is a PLL clock driver family, consisting of PI6CU877,

and PI6CUA877, developed for Registered DDR2

applications with 1.8V operation and differential clock input and

output levels.

The device is a zero delay buffer that distributes a differential

clock input pair (CLK, CLK) to eleven differential pairs of clock

outputs which includes feedback clock (Y[0:9], Y[0:9]; FBOUT,

FBOUT).

The clock outputs are controlled by CLK/CLK, FBOUT, FBOUT, the

LVCMOS inputs (OE, OS) and the Analog Power input (AV

When OE is LOW the outputs except FBOUT, FBOUT, are disabled

while the internal PLL continues to maintain its locked-in frequency.

OS is a pin that must be tied to GND or V

will function as described above. When OS is LOW, OE has no

effect on Y7/Y7, they are free running. When AV

the PLL is turned off and bypassed for test purposes.

When CLK/CLK are logic low, the device will enter a low power

mode. An input logic detection circuit will detect the logic low level

and perform a low power state where all Y[0:9], Y[0:9]; FBOUT,

FBOUT, and PLL are OFF.

PI6CUx877 is a high-performance, low skew, and low jitter PLL

clock driver, and it is also able to track Spread Spectrum Clocking

(SSC) for reduced EMI.

PLL Clock Driver for

1.8V DDR2 Mem o ry

DD.

When OS is high, OE

PI6CUA877

PS8689G

PI6CU877

is grounded,

DIMM

01/17/06

Related parts for PI6CU877NFE

PI6CU877NFE Summary of contents

Page 1

Features • PLL clock distribution optimized for DDR2-667/533/400 SDRAM applications. • Distributes one differential clock input pair to eleven differ- ential clock output pairs. • Differential Inputs (CLK, CLK) and (FBIN, FBIN) • Input OE/OS: LVCMOS • Differential Outputs (Y[0:9], ...

Page 2

Block Diagram 10K - 100kΩ FBIN FBIN * The Logic Detect (LD) powers down the device when a logic low is applied to both CK and CK. 08-0298 LD Powerdown Control & ...

Page 3

Pinout Table Pin Name Characteristics AGND Ground AV 1.8V nominal DD CK Differential Input CK Differential Input FB Differential Input IN FB Differential Input IN FB Differential Output OUT FB Differential Output OUT OE LVCMOS input OS LVCMOS input GND ...

Page 4

Absolute Maximum Ratings (Over operating free-air temperature range) Symbol I/O supply voltage range and analog /core supply voltage range DDQ VDD VDD V Input voltage range I V Output voltage range O I ...

Page 5

FCK Clock Frequency Specifi cations PI6CUx877 Operating Clock Frequency Part Number Min PI6CU877 125 PI6CUA877 125 Notes: 1. The PLL is able to handle spread spectrum induced skew. 2. Operating clock frequency indicates a range over which the PLL is ...

Page 6

DC Specifi cations Param- Description eter V All Inputs IK V HIGH output voltage OH I Output disabled low current ODL Output differential voltage, the magnitude of the difference V between the true and complimentary outputs, see ...

Page 7

AC Specifi cations Switching char ac ter is tics over rec om mend ed operating free-air temperature range (unless oth er wise noted) Parameter Description ten OE to and Y/Y tdis OE to and Y/Y tjit(cc+) Cycle-to-cycle jitter tjit(cc-) (11) ...

Page 8

60Ω L= 2.97" Z= 60Ω L= 2.97" PI6CxU877 GND 60Ω L= 2.97" Z= 60Ω L= 2.97" PI6CUx877 – 08-0298 PI6CUx877 R = 60Ω 60Ω V ...

Page 9

Figure ...

Page 10

Figure 7. Period Jitter (fo = average input frequency measured at CK/CK) �� 08-0298 � �� ...

Page 11

OE Y Figure 11. Time Delay Between Output Enable (OE) and Clock Output (Y, Y) 08-0298 � �� Figure 10. Dynamic Phase Offset ...

Page 12

... Packaging Mechanical: 52-Ball VFBGA (NF) (1,2) Ordering Information Ordering Code PI6CU877NFE PI6CUA877NFE Notes: 1. Thermal characteristics can be found on the company web site at http://www.pericom.com/packaging Pb-free and Green Pericom Semiconductor Corporation • 1-800-435-2336 • http://www.pericom.com 08-0298 Package Code NF Pb-free & Green, 52-ball VFBGA NF Pb-free & ...

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