ICS9250BF-12LFT IDT, Integrated Device Technology Inc, ICS9250BF-12LFT Datasheet - Page 2

• Manufacturer Part Number: ICS9250BF-12LFT
• Description: IC FREQ TIMING GENERATOR 56-SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Frequency Generatorr

Specifications of ICS9250BF-12LFT

• Frequency - Max: 133MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-SSOP
• Frequency-max: 133MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Output: -
• Input: -
• Other names: 9250BF-12LFT

ICS9250-12
Pin Descriptions
1
2, 3
4
5
6
7, 13, 19
8
9, 11, 12, 14, 15,
17, 18
10, 16
20, 24
21, 22, 25, 26
23, 27
28
29
30
31
32, 33
34
35
36
37
38
39
43, 47
40, 44
41, 42, 45, 46
48
49, 50
51
52
53, 54, 55
56
Pin number
GNDREF
REF(0:1)
VDDREF
X1
X2
GNDPCI
PCICLK_F
PCICLK[1:7]
VDDPCI
GND66
3V66[0:3]
VDD66
SEL 133/100#
GND48
48MHz
VDD48
SEL[0:1]
SPREAD#
PD#
CPU_STOP#
PCI_STOP#
GNDCOR
VDDCOR
VDDLCPU
GNDLCPU
CPUCLK[0:3]
GNDLCPU/2
CPU/2[0:1]
VDDLCPU/2
GNDLIOAPIC
IOAPIC[0:2]
VDDLIOAPIC
Pin name
PWR
OUT
PWR
IN
OUT
PWR
OUT
OUT
PWR
PWR
OUT
PWR
IN
PWR
OUT
PWR
IN
IN
IN
IN
IN
PWR
PWR
PWR
PWR
OUT
PWR
OUT
PWR
PWR
OUT
PWR
Type
Gnd pin for REF clocks
14.318MHz reference clock outputs at 3.3V
Power pin for REF clocks
XTAL_IN 14.318MHz crystal input
XTAL_OUT Crystal output
Gnd pin for PCICLKs
Free running PCI clock at 3.3V. Synchronous to CPU clocks. Not affected
by the PCI_STOP# input.
PCI clock outputs at 3.3V. Synchronous to CPU clocks.
3.3Volts power pin for PCICLKs
Gnd pin for 3V66 outputs
66MHz outputs at 3.3V. These outputs are stopped when CPU_STOP# is
driven active..
power pin for the 3V66 clocks.
This selects the frequency for the CPU and CPU/2 outputs. High =
133MHz, Low=100MHz
Ground pin for the 48MHz output
Fixed 48MHz clock output. 3.3V
Power pin for the 48MHz output.
Function select pins. See truth table for details.
Enables spread spectrum when active(Low). modulates all the CPU, PCI,
IOAPIC, 3V66 and CPU/2 clocks. Does not affect the REF and 48MHz
clocks. 0.5% down spread modulation.
This asynchronous input powers down the chip when drive active(Low).
The internal PLLs are disabled and all the output clocks are held at a Low
state.
This asychronous input halts the CPUCLK[0:3] and the 3V66[0:3] clocks at
logic "0" when driven active(Low). Does not affect the CPU/2 clocks.
This asynchronous input halts the PCICLK[1:7] at logic"0" when driven
active(Low). PCICLK_F is not affected by this input.
Ground pin for the PLL core
Power pin for the PLL core. 3.3V
Power pin for the CPUCLKs. 2.5V
Ground pin for the CPUCLKs
Host bus clock output at 2.5V. 133MHz or 100MHz depending on the state
of the SEL 133/100MHz.
Ground pin for the CPU/2 clocks.
2.5V clock outputs at 1/2 CPU frequency. 66MHz or50MHz depending on
the state of the SEL 133/100# input pin.
Power pin for the CPU/2 clocks. 2.5V
Ground pin for the IOAPIC outputs.
IOAPIC clocks at 2.5V. Synchronous with CPUCLKs but fixed at
16.67MHz.
Power pin for the IOAPIC outputs. 2.5V.
Description