DS26502LN+ Maxim Integrated Products, DS26502LN+ Datasheet - Page 81
![IC T1/E1/J1 64KCC ELEMENT 64LQFP](/photos/6/50/65017/64-lqfp_21-0083_sml.jpg)
DS26502LN+
Manufacturer Part Number
DS26502LN+
Description
IC T1/E1/J1 64KCC ELEMENT 64LQFP
Manufacturer
Maxim Integrated Products
Type
BITS Elementr
Datasheet
1.DS26502LN.pdf
(125 pages)
Specifications of DS26502LN+
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Frequency-max
-
Output
-
Input
-
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DS26502 T1/E1/J1/64KCC BITS Element
automatically be placed in the receive path. The jitter attenuator can also be disabled (in effect, removed)
by setting the DJA bit (LIC1.1). Either the recovered clock from the clock/data recovery block or the
clock applied at the TCLK pin is adjusted to create a smooth jitter-free clock that is used to clock data out
of the jitter attenuator FIFO. It is acceptable to provide a gapped/bursty clock at the TCLK pin if the
jitter attenuator is placed on the transmit side. If the incoming jitter exceeds either 120 UI
(buffer
P-P
depth is 128 bits) or 28 UI
(buffer depth is 32 bits), then the DS26502 will divide the internal nominal
P-P
32.768MHz (E1) or 24.704MHz (T1) clock by either 15 or 17 instead of the normal 16 to keep the buffer
from overflowing. When the device divides by either 15 or 17, it also sets the Jitter Attenuator Limit Trip
(JALT) bit in Status Register 1 (SR1.4).
13.6 CMI (Code Mark Inversion) Option
The DS26502 provides a CMI interface for connection to optical transports. This interface is a unipolar
1T2B type of signal. Ones are encoded as either a logical one or zero level for the full duration of the
clock period. Zeros are encoded as a zero-to-one transition at the middle of the clock period.
Figure 13-3. CMI Coding
CLOCK
1
1
0
1
0
0
1
DATA
CMI
Transmit and receive CMI is enabled via LIC4.7. When this register bit is set, the TTIP pin will output
CMI-coded data at normal levels. This signal can be used to directly drive an optical interface. When
CMI is enabled, the user can also use HDB3/B8ZS coding. When this register bit is set, the RTIP pin will
become a unipolar CMI input. The CMI signal will be processed to extract and align the clock with data.
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