LCMXO2-1200HC-4TG100CR1 Lattice, LCMXO2-1200HC-4TG100CR1 Datasheet - Page 102
![no-image](/images/manufacturer_photos/0/3/380/lattice_sml.jpg)
LCMXO2-1200HC-4TG100CR1
Manufacturer Part Number
LCMXO2-1200HC-4TG100CR1
Description
IC PLD 1280LUTS 80I/O 100TQFP
Manufacturer
Lattice
Datasheet
1.LCMXO2-1200HC-4TG100CR1.pdf
(103 pages)
Specifications of LCMXO2-1200HC-4TG100CR1
Programmable Type
*
Number Of Macrocells
*
Voltage - Input
*
Speed
*
Mounting Type
*
Package / Case
*
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
220-1135
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LCMXO2-1200HC-4TG100CR1
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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© 2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
November 2010
For Further Information
A variety of technical notes for the MachXO2 family are available on the Lattice web site.
• TN1198,
• TN1199,
• TN1200,
• TN1201,
• TN1202,
• TN1203,
• TN1204,
• TN1205,
• TN1206,
• TN1207,
• TN1074,
• TN1087,
• AN8066,
• MachXO2 Device Pinout Files
•
• Lattice design tools
• Stand-alone Power Calculator for MachXO2 Devices
For further information on interface standards, refer to the following web sites:
• JEDEC Standards (LVTTL, LVCMOS, LVDS, DDR, DDR2, LPDDR): www.jedec.org
• PCI: www.pcisig.com
Thermal Management
Power Estimation and Management for MachXO2 Devices
MachXO2 sysCLOCK PLL Design and Usage Guide
MachXO2 Density Migration
Memory Usage Guide for MachXO2 Devices
MachXO2 sysIO Usage Guide
Implementing High-Speed Interfaces with MachXO2 Devices
MachXO2 Programming and Configuration Usage Guide
Using User Flash Memory and Hardened Control Functions in MachXO2 Devices
MachXO2 SED Usage Guide
Using TraceID in MachXO2 Devices
PCB Layout Recommendations for BGA Packages
Minimizing System Interruption During Configuration Using TransFR Technology
Boundary Scan Testability with Lattice sysIO Capability
document
MachXO2 Family Data Sheet
6-1
Supplemental Information
Preliminary Data Sheet DS1035
DS1035
Further Info_01.0
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