MC14LC5480SDR2 Freescale, MC14LC5480SDR2 Datasheet - Page 3

• Manufacturer Part Number: MC14LC5480SDR2
• Manufacturer: Freescale
• Type: PCMr

Specifications of MC14LC5480SDR2

• Number Of Channels: 1
• Gain Control: Adjustable
• Number Of Adc's: 1
• Number Of Dac's: 1
• Adc/dac Resolution: 13b
• Package Type: SSOP
• Sample Rate: 8KSPS
• Number Of Adc Inputs: 1
• Number Of Dac Outputs: 1
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Pin Count: 20
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

POWER SUPPLY
V DD
Positive Power Supply (Pin 6)
nected to + 5 V. This pin should be decoupled to V SS with a
0.1 F ceramic capacitor.
V SS
Negative Power Supply (Pin 15)
connected to 0 V.
V AG
Analog Ground Output (Pin 20)
ulated to 2.4 V. This pin should be decoupled to V SS with a
0.01 F to 0.1 F ceramic capacitor. All analog signal pro-
cessing within this device is referenced to this pin. If the au-
dio signals to be processed are referenced to V SS , then
special precautions must be utilized to avoid noise between
V SS and the V AG pin. Refer to the applications information in
this document for more information. The V AG pin becomes
high impedance when this device is in the powered down
mode.
CONTROL
Mu/A
Mu/A Law Select (Pin 16)
expansion for the decoder. Mu–Law companding is selected
when this pin is connected to V DD and A–Law companding is
selected when this pin is connected to V SS .
PDI
Power–Down Input (Pin 10)
when a logic 0 is applied. When this device is powered down,
all of the clocks are gated off and all bias currents are turned
off, which causes RO+, RO–, PO–, PO+, TG, V AG , and DT to
become high impedance. The device will operate normally
when a logic 1 is applied to this pin. The device goes through
a power–up sequence when this pin is taken to a logic 1
state, which prevents the DT PCM output from going low im-
pedance for at least two FST cycles. The filters must settle
out before the DT PCM output or the RO+ or RO– receive
analog outputs will represent a valid analog signal.
ANALOG INTERFACE
TI+
Transmit Analog Input (Non–Inverting) (Pin 19)
setting operational amplifier. This pin accommodates a differ-
ential to single–ended circuit for the input gain setting op
amp. This allows input signals that are referenced to the V SS
pin to be level shifted to the V AG pin with minimum noise.
This pin may be connected to the V AG pin for an inverting
amplifier configuration if the input signal is already refer-
enced to the V AG pin. The common mode range of the TI+
and TI– pins is from 1.2 V, to V DD minus 2 V. This is an FET
gate input. Connecting the TI+ pin to V DD will place this am-
This is the most positive power supply and is typically con-
This is the most negative power supply and is typically
This output pin provides a mid–supply analog ground reg-
This pin controls the compression for the encoder and the
This pin puts the device into a low power dissipation mode
This is the non–inverting input of the transmit input gain
PIN DESCRIPTIONS
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
plifier’s output (TG) into a high–impedance state, thus allow-
ing the TG pin to serve as a high–impedance input to the
transmit filter.
TI–
Transmit Analog Input (Inverting) (Pin 18)
erational amplifier. Gain setting resistors are usually con-
nected from this pin to TG and from this pin to the analog
signal source. The common mode range of the TI+ and TI–
pins is from 1.2 V to V DD – 2 V. This is an FET gate input.
Connecting the TI+ pin to V DD will place this amplifier’s out-
put (TG) into a high–impedance state, thus allowing the TG
pin to serve as a high–impedance input to the transmit filter.
TG
Transmit Gain (Pin 17)
amplifier and the input to the transmit band–pass filter. This
op amp is capable of driving a 2 k load. Connecting the TI+
pin to V DD will place this amplifier’s output (TG) into a high–
impedance state, thus allowing the TG pin to serve as a
high–impedance input to the transmit filter. All signals at this
pin are referenced to the V AG pin. This pin is high impedance
when the device is in the powered down mode.
RO+
Receive Analog Output (Non–Inverting) (Pin 1)
filter from the digital–to–analog converter. This output is
capable of driving a 2 k load to 1.575 V peak referenced to
the V AG pin. This pin is high impedance when the device is in
the powered down mode.
RO–
Receive Analog Output (Inverting) (Pin 2)
from the digital–to–analog converter. This output is capable
of driving a 2 k load to 1.575 V peak referenced to the V AG
pin. This pin is high impedance when the device is in the
powered down mode.
PI
Power Amplifier Input (Pin 3)
inverting input to the PO– amplifier is internally tied to the
V AG pin. The PI and PO– pins are used with external resis-
tors in an inverting op amp gain circuit to set the gain of the
PO+ and PO– push–pull power amplifier outputs. Connect-
ing PI to V DD will power down the power driver amplifiers and
the PO+ and PO– outputs will be high impedance.
PO–
Power Amplifier Output (Inverting) (Pin 4)
to provide a feedback signal to the PI pin to set the gain of
the push–pull power amplifier outputs. This pin is capable of
driving a 300
differential (push–pull) and capable of driving a 300
3.15 V peak, which is 6.3 V peak–to–peak. The bias voltage
and signal reference of this output is the V AG pin. The V AG
pin cannot source or sink as much current as this pin, and
This is the inverting input of the transmit gain setting op-
This is the output of the transmit gain setting operational
This is the non–inverting output of the receive smoothing
This is the inverting output of the receive smoothing filter
This is the inverting input to the PO– amplifier. The non–
This is the inverting power amplifier output, which is used
load to PO+. The PO+ and PO– outputs are
load to