NB100LVEP224FAR2G ON Semiconductor, NB100LVEP224FAR2G Datasheet - Page 7

• Manufacturer Part Number: NB100LVEP224FAR2G
• Manufacturer: ON Semiconductor
• Type: Clock Driverr

Specifications of NB100LVEP224FAR2G

• Number Of Clock Inputs: 2
• Mode Of Operation: Differential
• Output Frequency: >1000MHz
• Output Logic Level: ECL
• Operating Supply Voltage (min): -2.375/2.375V
• Operating Supply Voltage (typ): -2.5/-3.3/2.5/3.3V
• Operating Supply Voltage (max): -3.8/3.8V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Signal Type: ECL/LVDS/PECL
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Compliant

Using the thermally enhanced package of the
NB100LVEP224
LQFP package. The package is molded so that a portion of
the leadframe is exposed at the surface of the package
bottom side. This exposed metal pad will provide the low
thermal impedance that supports the power consumption of
the NB100LVEP224 high-speed bipolar integrated circuit
and will ease the power management task for the system
design. In multilayer board designs, a thermal land pattern
on the printed circuit board and thermal vias are
recommended to maximize both the removal of heat from
the
NB100LVEP224. The size of the land pattern can be larger,
smaller, or even take on a different shape than the exposed
pad on the package. However, the solderable area should be
at least the same size and shape as the exposed pad on the
package. Direct soldering of the exposed pad to the thermal
land will provide an efficient thermal conduit. The thermal
vias will connect the exposed pad of the package to internal
copper planes of the board. The number of vias, spacing, via
diameters and land pattern design depend on the application
and the amount of heat to be removed from the package.
when an array of vias is incorporated in the land pattern.
NB100LVEP224 applications on multi-layer boards
comprises a 4 X 4 thermal via array using a 1.2 mm pitch as
shown in Figure 7 providing an efficient heat removal path.
1 oz. copper via barrel plating. Solder wicking inside the via
may result in voiding during the solder process and must be
avoided. If the copper plating does not plug the vias, stencil
print solder paste onto the printed circuit pad. This will
The NB100LVEP224 uses a thermally enhanced 64-lead
Maximum thermal and electrical performance is achieved
The
The via diameter should be approximately 0.3 mm with
Thermal Via Array (4 X 4)
1.2 mm Pitch
0.3 mm Diameter
Figure 7. Recommended Thermal Land Pattern
package
4.6
recommended
and
electrical
thermal
4.6
performance
land
Exposed Pad
Land Pattern
APPLICATIONS INFORMATION
All Units mm
design
of
NB100LVEP224
http://onsemi.com
the
for
7
supply enough solder paste to fill those vias and not starve
the solder joints. The attachment process for the exposed pad
package is equivalent to standard surface mount packages.
Figure 8, “Recommended solder mask openings”, shows a
recommended solder mask opening with respect to a 4 X 4
thermal via array. Because a large solder mask opening may
result in a poor rework release, the opening should be
subdivided as shown in Figure 8. For the nominal package
standoff of 0.1 mm, a stencil thickness of 5 to 8 mils should
be considered.
operation. This is especially true for high-fanout and high
output drive capability products.
calculation the thermal resistance parameters of the package
is provided:
* Junction to ambient and Junction to board, four-conductor
layer test board (2S2P) per JESD 51-8
only. It is therefore recommended that users employ
sufficient thermal modeling analysis to assist in applying the
general recommendations to their particular application to
assure adequate thermal performance. The exposed pad of
the NB100LVEP224 package is electrically shorted to the
substrate of the integrated circuit and V
should be electrically connected to V
Table 9. Thermal Resistance *
Proper thermal management is critical for reliable system
For thermal system analysis and junction temperature
These recommendations are to be used as a guideline,
Thermal Via Array (4 X 4)
1.2 mm Pitch
0.3 mm Diameter
Figure 8. Recommended Solder Mask Openings
4.6
lfpm
100
500
0
0.2
0.2
qJA 5C/W
35.6
32.8
30.0
4.6
1.0
EE
EE
1.0
.
. The thermal land
Exposed Pad
Land Pattern
qJC 5C/W
All Units mm
3.2
4.9
6.4