SCAN926260TUF National Semiconductor, SCAN926260TUF Datasheet - Page 12

• Manufacturer Part Number: SCAN926260TUF
• Manufacturer: National Semiconductor

Specifications of SCAN926260TUF

• Number Of Elements: 6
• Input Type: CMOS/TTL
• Operating Supply Voltage (typ): 3.3V
• Differential Input High Threshold Voltage: 50mV
• Diff. Input Low Threshold Volt: -50mV
• Output Type: Deserializer
• Transmission Data Rate: 660Mbps
• Power Dissipation: 3.7W
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: LBGA
• Number Of Receivers: 1
• Number Of Drivers: 10
• Lead Free Status / RoHS Status: Not Compliant

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Application Information
USING THE SCAN926260
The SCAN926260 combines six 1:10 deserializers into a sin-
gle chip. Each of the six deserializers accepts a BusLVDS
data stream up to 660 Mbps from one of National
Semiconductor's 10-Bit Serializers. The Deserializers then
recover the embedded two clock bits and data to deliver the
resulting 10-bit wide words to the output. The Deserializer
uses a separate reference clock (REFCLK) and an on-board
PLL to extract the clock information from the incoming data
stream and then deserialize the data. The Deserializer mon-
itors the incoming clock information, determines lock status,
and asserts the LOCKn output high when loss of lock occurs.
POWER CONSIDERATIONS
An all CMOS design of the Deserializer makes it an inherently
low power device.
POWERING UP THE DESERIALIZER
The SCAN926260 can be powered up at any time. The RE-
FCLK input can be running before the Deserializer powers up,
and it must be running in order for the Deserializer to lock to
incoming data. The Deserializer outputs (ROUTn[0:9]), the
recovered clock (RCLKn), and LOCKn are high until the De-
serializer detects data transmission at its inputs and locks to
the incoming data stream.
DATA TRANSFER
Once the Deserializer powers up, it must be phase locked to
the transmitter to transfer data. Phase locking occurs when
the Deserializer locks to incoming data or when the Serializer
sends sync patterns. The Serializer sends SYNC patterns
whenever the SYNC1 or SYNC2 inputs are high. The
LOCKn output of the Deserializer remains high until it has
locked to the incoming data stream. Connecting the LOCKn
output of the Deserializer to one of the SYNC inputs of the
Serializer will guarantee that enough SYNC patterns are sent
to achieve Deserializer lock.
The Deserializer can also lock to incoming data by simply
powering up the device and allowing the “lock to pseudo ran-
dom data” circuitry to find and lock to the data stream.
While the Deserializer LOCKn output is low, data at the re-
spective channel’s Deserializer outputs (ROUTn[0:9]) is valid,
except for the specific case when loss of lock occurs during
transmission which is further discussed in the "Recovering
from LOCK Loss" section below.
NOISE MARGIN
The Deserializer noise margin is the amount of input jitter
(phase noise) that the Deserializer can tolerate and still reli-
ably receive data. Various environmental and systematic fac-
tors include:
of-band noise)
Please see the section on "Using t
Quality" for more information.
RECOVERING FROM LOCK LOSS
In the case where the Deserializer loses lock during data
transmission, up to 1 cycle of data that was previously re-
ceived can be invalid. This is due to the delay in the lock
detection circuit. The lock detect circuit requires that invalid
clock information be received two times in a row to indicate
Serializer: TCLK jitter, V
Media: ISI, Large V
Deserializer: V
DD
noise
CM
shifts
DD
noise (noise bandwidth and out-
RNM
to Validate Signal
12
loss of lock. Since clock information has been lost, it is pos-
sible that data was also lost during these cycles. Therefore,
after the Deserializer relocks to the incoming data stream and
the Deserializer LOCKn pin goes low, at least one previous
data cycle should be suspect for bit errors.
The Deserializer can relock to the incoming data stream by
making the Serializer resend SYNC patterns, as described
above, or by locking to pseudo random data, which can take
more time, depending on the data patterns being received.
HOT INSERTION
All Bus LVDS Deserializers are hot pluggable if you follow a
few rules. When inserting, ensure the Ground pin(s) makes
contact first, then the VCC pin(s), and then the I/O pins. When
removing, the I/O pins should be unplugged first, then the
VCC, then the Ground. Random lock hot insertion is illustrat-
ed in Figure 9.
TRANSMISSION MEDIA
The Serializer and Deserializer can also be used in point-to-
point configurations, through PCB trace, through twisted pair
cable, or twinax cables. In point-to-point configurations, the
transmission media need only be terminated at the receiver
end. Please note that in point-to-point configurations, the po-
tential of offsetting the ground levels of the Serializer vs. the
Deserializer must be considered. In some applications, mul-
tidrop configurations may be possible. Bus LVDS provides a
±1.0V common mode range at the receiver inputs.
FAILSAFE BIASING FOR THE SCAN926260
The SCAN926260 has internal failsafe biasing and an im-
proved input threshold sensitivity of ±50mV versus ±100mV
for the DS92LV1210.. This allows for a greater differential
noise margin. However, in cases where the receiver input is
not being actively driven, the increased sensitivity of the
SCAN926260 can pickup noise as a signal and cause unin-
tentional locking. For example, this can occur when an input
cable is disconnected.
External resistors can be added to the receiver circuit board
to boost the level of failsafe biasing. Typically, the non-invert-
ing receiver input is pulled up and the inverting receiver input
is pulled down by high value resistors. The pull-up and pull-
down resistors (R
termination resistor (R
when they are not connected to an active driver. The value of
the pull-up and pull-down resistors should be chosen so that
enough current is drawn to provide a +15mV minimum drop
across the termination resistor in the presence of anticipated
input noise. Also, in systems where use of the individual
channel is well known or controlled, using the respective
channel’s PWRDWNn pin(s) may eliminate the need for ex-
FIGURE 9. Hot Insertion Lock to Pseudo-Random Data
1
and R
L
) which biases the receiver inputs
2
) provide a current path through the
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