LFXP3E-3TN100C LATTICE SEMICONDUCTOR, LFXP3E-3TN100C Datasheet - Page 19
LFXP3E-3TN100C
Manufacturer Part Number
LFXP3E-3TN100C
Description
FPGA LatticeXP Family 3000 Cells 320MHz 130nm (CMOS) Technology 1.2V 100-Pin TQFP Tray
Manufacturer
LATTICE SEMICONDUCTOR
Datasheet
1.LFXP3C-3QN208C.pdf
(130 pages)
Specifications of LFXP3E-3TN100C
Package
100TQFP
Family Name
LatticeXP
Device Logic Units
3000
Maximum Internal Frequency
320 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
62
Ram Bits
55296
Re-programmability Support
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP3E-3TN100C
Manufacturer:
LATTICE
Quantity:
201
Company:
Part Number:
LFXP3E-3TN100C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
Figure 2-18. Group of Seven PIOs
Figure 2-19. DQS Routing
PIO
The PIO contains four blocks: an input register block, output register block, tristate register block and a control logic
block. These blocks contain registers for both single data rate (SDR) and double data rate (DDR) operation along
with the necessary clock and selection logic. Programmable delay lines used to shift incoming clock and data sig-
nals are also included in these blocks.
Input Register Block
The input register block contains delay elements and registers that can be used to condition signals before they are
passed to the device core. Figure 2-20 shows the diagram of the input register block.
Input signals are fed from the sysIO buffer to the input register block (as signal DI). If desired the input signal can
bypass the register and delay elements and be used directly as a combinatorial signal (INDD), a clock (INCK) and
Four PICs
DQS
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
2-16
Buffer
sysIO
Delay
Assigned DQS Pin
LatticeXP Family Data Sheet
PADA “T”
PADB “C”
PADA “T”
PADB “C”
PADA “T”
PADB “C”
PADA “T”
PADB “C”
PADA “T”
PADB “C”
PADA “T”
PADB “C”
PADA “T”
PADB “C”
PADB “C”
PADA “T”
PADB “C”
PADA “T”
PADA “T”
PADA “T”
PADB “C”
LVDS Pair
LVDS Pair
LVDS Pair
LVDS Pair
LVDS Pair
LVDS Pair
One PIO Pair
Architecture
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