LFEC6E-4FN256I LATTICE SEMICONDUCTOR, LFEC6E-4FN256I Datasheet - Page 16
LFEC6E-4FN256I
Manufacturer Part Number
LFEC6E-4FN256I
Description
FPGA LatticeEC Family 6100 Cells 378MHz 130nm (CMOS) Technology 1.2V 256-Pin FBGA
Manufacturer
LATTICE SEMICONDUCTOR
Datasheet
1.LFEC3E-5TN144C.pdf
(163 pages)
Specifications of LFEC6E-4FN256I
Package
256FBGA
Family Name
LatticeEC
Device Logic Units
6100
Maximum Internal Frequency
378 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
195
Ram Bits
94208
In System Programmability
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFEC6E-4FN256I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
Memory Cascading
Larger and deeper blocks of RAM can be created using EBR sysMEM Blocks. Typically, the Lattice design tools
cascade memory transparently, based on specific design inputs.
Single, Dual and Pseudo-Dual Port Modes
Figure 2-15 shows the four basic memory configurations and their input/output names. In all the sysMEM RAM
modes the input data and address for the ports are registered at the input of the memory array. The output data of
the memory is optionally registered at the output.
Figure 2-15. sysMEM EBR Primitives
The EBR memory supports three forms of write behavior for single port or dual port operation:
1. Normal – data on the output appears only during read cycle. During a write cycle, the data (at the current
2. Write Through – a copy of the input data appears at the output of the same port during a write cycle. This
3. Read-Before-Write – when new data is being written, the old content of the address appears at the output.
Memory Core Reset
The memory array in the EBR utilizes latches at the A and B output ports. These latches can be reset asynchro-
nously or synchronously. RSTA and RSTB are local signals, which reset the output latches associated with Port A
and Port B, respectively. The Global Reset (GSRN) signal resets both ports. The output data latches and associ-
ated resets for both ports are as shown in Figure 2-16.
address) does not appear on the output. This mode is supported for all data widths.
mode is supported for all data widths.
This mode is supported for x9, x18 and x36 data widths.
AD[12:0]
AD[12:0]
DI[35:0]
CS[2:0]
CS[2:0]
RST
RST
CLK
CLK
WE
CE
CE
Single Port RAM
ROM
EBR
EBR
DO[35:0]
DO[35:0]
2-13
ADW[12:0]
DOA[17:0]
ADA[12:0]
DIA[17:0]
CSA[2:0]
DI[35:0]
CS[2:0]
CLKW
CLKA
RSTA
CEW
WEA
CEA
RST
WE
Pseudo-Dual Port RAM
True Dual Port RAM
EBR
EBR
LatticeECP/EC Family Data Sheet
ADB[12:0]
DIB[17:0]
CEB
CLKB
RSTB
WEB
CSB[2:0]
DOB[17:0]
ADR[12:0]
DO[35:0]
CER
CLKR
Architecture
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