LC5512MV-75F256C LATTICE SEMICONDUCTOR, LC5512MV-75F256C Datasheet - Page 56

• Manufacturer Part Number: LC5512MV-75F256C
• Description: CPLD ispXPLD™ 5000MV Family 150K Gates 512 Macro Cells 150MHz EECMOS Technology 3.3V 256-Pin FBGA
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of LC5512MV-75F256C

• Package: 256FBGA
• Family Name: ispXPLD™ 5000MV
• Device System Gates: 150000
• Number Of Macro Cells: 512
• Maximum Propagation Delay Time: 7.5 ns
• Number Of User I/os: 193
• Typical Operating Supply Voltage: 3.3 V
• Maximum Operating Frequency: 150 MHz
• Number Of Product Terms Per Macro: 160
• Ram Bits: 262144
• Memory Type: EEPROM/SRAM
• Operating Temperature: 0 to 90 °C

Lattice Semiconductor
ispXPLD 5256MX Logic Signal Connections
sysIO Bank LVDS Pair
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
GCLK0N
GCLK0P
61N
61P
62N
62P
63N
63P
64N
64P
65N
65P
66N
66P
67N
67P
68N
68P
69N
69P
0N
1N
2N
3N
0P
1P
2P
3P
4P
-
-
-
-
-
-
-
-
-
-
-
-
-
Primary Macrocell/
H18/CLK_OUT0
H6/PLL_RST0
H4/PLL_FBK0
GND (Bank 0)
GND (Bank 1)
A10/DATA6
A12/DATA7
A14/INITB
A0/DATA0
A2/DATA1
A4/DATA2
A5/DATA3
A6/DATA4
A8/DATA5
Function
VCCO1
VCCO0
GCLK0
GCLK1
VCCJ
GND
GND
GND
VCC
TMS
TDO
TCK
H30
H28
H26
H24
H22
H21
H20
H16
H14
H12
H10
TDI
H8
H5
H2
H0
Macrocell 1
G17
G16
G15
G14
G13
G12
G11
G10
G9
G8
G7
G6
G5
G4
A0
A1
A2
A3
A4
A5
A6
A7
A8
52
Alternate Outputs
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Macrocell 2
ispXPLD 5000MX Family Data Sheet
H17
H16
H15
H14
H13
H12
H11
H10
H9
H7
H5
H4
H8
H6
B0
B1
B2
B3
B4
B5
B6
B7
B8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Alternate Input
H31
H29
H27
H25
H23
H19
H17
H15
H13
H11
A11
A13
A15
H9
H7
H3
H1
A1
A3
A7
A9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
See Power Supply and
NC Connections Table
GND (Bank 0)
GND (Bank 1)
Ball Number
256 fpBGA
VCCO0
VCCO1
GND
VCC
GND
GND
G1
G4
G3
G2
M1
B1
C1
D3
C2
E3
D2
E2
G5
H5
H3
H1
H2
H6
H4
K2
K3
K4
K5
F2
F1
F3
J5
L2
L3
J2
J6
J3
J4