MC9S12DP512CPVE Freescale, MC9S12DP512CPVE Datasheet - Page 55

• Manufacturer Part Number: MC9S12DP512CPVE
• Manufacturer: Freescale

Specifications of MC9S12DP512CPVE

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 25MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 14KB
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.25V
• Operating Supply Voltage (min): 2.35/4.5V
• On-chip Adc: 2(8-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Pin Name
Funct. 1
PT[7:0]
PS7
PS6
PS5
PS4
PS3
PS2
PS1
PS0
2.3 Detailed Signal Descriptions
2.3.1 EXTAL, XTAL — Oscillator Pins
EXTAL and XTAL are the crystal driver and external clock pins. On reset all the device clocks are derived
from the EXTAL input frequency. XTAL is the crystal output.
2.3.2 RESET — External Reset Pin
An active low bidirectional control signal, it acts as an input to initialize the MCU to a known start-up
state, and an output when an internal MCU function causes a reset.
2.3.3 TEST — Test Pin
This input only pin is reserved for test.
2.3.4 VREGEN — Voltage Regulator Enable Pin
This input only pin enables or disables the on-chip voltage regulator.
NOTE:
Pin Name
Funct. 2
IOC[7:0]
MOSI0
MISO0
RXD1
RXD0
SCK0
TXD1
TXD0
SS0
The TEST pin must be tied to VSS in all applications.
Pin Name
Funct. 3
—
—
—
—
—
—
—
—
—
Pin Name
Funct. 4
—
—
—
—
—
—
—
—
—
Pin Name
Funct. 5
—
—
—
—
—
—
—
—
—
Supply
Power
VDDX
VDDX
PERS/
CTRL
PERT/
PPSS
PPST
Internal Pull
Resistor
Disabled Port T I/O, Timer channels
MC9S12DP512 Device Guide V01.25
Reset
State
Up
Port S I/O, SS of SPI0
Port S I/O, SCK of SPI0
Port S I/O, MOSI of SPI0
Port S I/O, MISO of SPI0
Port S I/O, TXD of SCI1
Port S I/O, RXD of SCI1
Port S I/O, TXD of SCI0
Port S I/O, RXD of SCI0
Description
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