CY7C429-25VC Cypress Semiconductor Corp, CY7C429-25VC Datasheet - Page 11

• Manufacturer Part Number: CY7C429-25VC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C429-25VC

• Density: 16Kb
• Word Size: 9b
• Sync/async: Asynchronous
• Expandable: Yes
• Package Type: SOJ
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 28
• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-06001 Rev. *B
Switching Waveforms
Architecture
The
CY7C432/3 FIFOs consist of an array of 256, 512, 1024, 2048,
4096 words of 9 bits each (implemented by an array of
dual-port RAM cells), a read pointer, a write pointer, control
signals (W, R, XI, XO, FL, RT, MR), and Full, Half Full, and
Empty flags.
Dual-Port RAM
The dual-port RAM architecture refers to the basic memory
cell used in the RAM. The cell itself enables the read and write
operations to be independent of each other, which is
necessary to achieve truly asynchronous operation of the
inputs and outputs. A second benefit is that the time required
to increment the read and write pointers is much less than the
time that would be required for data propagation through the
memory, which would be the case if the memory were imple-
mented using the conventional register array architecture.
Expansion Timing Diagrams
Note:
15. Expansion Out of device 1 (XO
XO
XO
1
1
CY7C419,
(XI
(XI
Q
D
0
0
2
2
–Q
–D
)
)
[15]
[15]
W
R
8
8
CY7C420/1,
READ FROM LAST PHYSICAL
1
LOCATION OF DEVICE 1
t
) is connected to Expansion In of device 2 (XI
LZR
(continued)
t
XOL
WRITE TO LAST PHYSICAL
t
A
LOCATION OF DEVICE 1
CY7C424/5,
t
XOL
t
DATA
VALID
DVR
CY7C428/9,
DATA VALID
t
SD
t
RR
t
t
XOH
HD
t
WR
2
).
Resetting the FIFO
Upon power-up, the FIFO must be reset with a Master Reset
(MR) cycle. This causes the FIFO to enter the empty condition
signified by the Empty flag (EF) being LOW, and both the Half
Full (HF) and Full flags (FF) being HIGH. Read (R) and write
(W) must be HIGH t
edge of MR for a valid reset cycle. If reading from the FIFO
after a reset cycle is attempted, the outputs will all be in the
high-impedance state.
Writing Data to the FIFO
The availability of at least one empty location is indicated by a
HIGH FF. The falling edge of W initiates a write cycle. Data
appearing at the inputs (D
rising edge of W will be stored sequentially in the FIFO.
The EF LOW-to-HIGH transition occurs t
LOW-to-HIGH transition of W for an empty FIFO. HF goes
LOW t
actually being Half Full. Therefore, the HF is active once the
t
READ FROM FIRST PHYSICAL
XOH
LOCATION OF DEVICE 2
WRITE TO FIRST PHYSICAL
WHF
LOCATION OF DEVICE 2
after the falling edge of W following the FIFO
t
A
RPW
/t
CY7C419/21/25/29/33
WPW
DATA VALID
0
t
SD
–D
VALID
DATA
before and t
8
) t
t
DVR
SD
before and t
t
HD
t
HZR
RMR
WEF
Page 11 of 25
after the rising
after the first
HD
after the
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