K4H561638F-UC/LAA Samsung Semiconductor, K4H561638F-UC/LAA Datasheet - Page 3
![no-image](/images/manufacturer_photos/0/5/578/samsung_semiconductor_sml.jpg)
K4H561638F-UC/LAA
Manufacturer Part Number
K4H561638F-UC/LAA
Description
Manufacturer
Samsung Semiconductor
Datasheet
1.K4H561638F-UCLAA.pdf
(23 pages)
Specifications of K4H561638F-UC/LAA
Lead Free Status / RoHS Status
Compliant
DDR SDRAM 256Mb F-die (x8, x16) Pb-Free
Key Features
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe
• Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• LDM,UDM for write masking only (x16)
• Auto & Self refresh
• 7.8us refresh interval(8K/64ms refresh)
• Maximum burst refresh cycle : 8
• 66pin TSOP II
• RoHS compliant
Operating Frequencies
*CL : CAS Latency
Ordering Information
-. Read latency 2, 2.5 (clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
K4H561638F-UC/LB3
K4H561638F-UC/LAA
K4H561638F-UC/LA2
K4H561638F-UC/LB0
K4H560838F-UC/LB3
K4H560838F-UC/LAA
K4H560838F-UC/LA2
K4H560838F-UC/LB0
Speed @CL2.5
Speed @CL2
Part No.
Pb-Free
package
L(U)DQS
B3(DDR333@CL=2.5)
16M x 16
32M x 8
133MHz
166MHz
Org.
B3(DDR333@CL=2.5)
AA(DDR266@CL=2)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
B3(DDR333@CL=2.5)
AA(DDR266@CL=2)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
AA(DDR266@CL=2.0)
Max Freq.
133MHz
133MHz
A2(DDR266@CL=2.0)
133MHz
133MHz
Interface
SSTL2
SSTL2
Rev. 1.2 October, 2004
B0(DDR266@CL=2.5)
DDR SDRAM
66pin TSOP II
66pin TSOP II
100MHz
133MHz
Package