MT46V128M8P-5B:A Micron Technology Inc, MT46V128M8P-5B:A Datasheet - Page 67

• Manufacturer Part Number: MT46V128M8P-5B:A
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46V128M8P-5B:A

• Organization: 128Mx8
• Density: 1Gb
• Address Bus: 16b
• Access Time (max): 700ps
• Maximum Clock Rate: 400MHz
• Operating Supply Voltage (typ): 2.6V
• Package Type: TSOP
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.5V
• Supply Current: 235mA
• Pin Count: 66
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

Figure 38:
Figure 39:
PDF: 09005aef80a2f898/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/07 EN
Nonconsecutive WRITE-to-WRITE
Random WRITE Cycles
Notes:
Notes:
t DQSS (NOM)
Command
1. DI b (or n) = data-in from column b (or column n).
2. Three subsequent elements of data-in are applied in the programmed order following DI b.
3. Three subsequent elements of data-in are applied in the programmed order following DI n.
4. An uninterrupted burst of 4 is shown.
5. Each WRITE command may be to any bank.
1. DI b (or x or n or a or g) = data-in from column b (or column x, or column n, or column a, or
2. b', x', n', a' or g' indicate the next data-in following DO b, DO x, DO n, DO a, or DO g,
3. Programmed BL = 2, BL = 4, or BL = 8 in cases shown.
4. Each WRITE command may be to any bank.
Address
Command
Address
column g).
respectively.
DQS
CK#
DM
DQ
CK
DQS
CK#
DM
DQ
CK
WRITE
Bank,
Col b
T0
WRITE
Bank,
Col b
T0
t DQSS (NOM)
t DQSS
WRITE
Bank,
Col x
DI
T1
b
NOP
DI
T1
b
67
T1n
DI
b'
T1n
WRITE
Bank,
Col n
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T2
DI
x
NOP
T2
T2n
DI
x'
T2n
1Gb: x4, x8, x16 DDR SDRAM
WRITE
Bank,
Col a
WRITE
T3
DI
Bank,
Col n
n
T3
Transitioning Data
T3n
DI
n'
Transitioning Data
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WRITE
Bank,
Col g
T4
DI
NOP
DI
a
T4
n
T4n
T4n
DI
a'
Operations
T5
NOP
DI
T5
NOP
g
Don’t Care
Don’t Care
T5n
T5n
DI
g'