AD9954ASV Analog Devices Inc, AD9954ASV Datasheet - Page 18

• Manufacturer Part Number: AD9954ASV
• Manufacturer: Analog Devices Inc

Specifications of AD9954ASV

• Lead Free Status / RoHS Status: Not Compliant

AD9954
Table 8. Internal Profile Control
CFR1<29:27>
(Binary)
000
001
010
011
100
101
110
111
A single-burst mode is one in which the composite sweep is
executed once. For example, assume the device is programmed
for ramp-up mode and the CFR1<29:27> bits are written to
Logic 010(b). Upon receiving an I/O update, the internal
control logic signals the device to begin executing the ramp-up
mode sequence for Profile 0. Upon reaching the RAM segment
final address value for Profile 0, the device jumps to the beginning
address of Profile 1 and begins executing that ramp-up sequence.
Upon reaching the RAM segment final address value for
Profile 1, the device jumps to the beginning address of Profile 2
and begins executing that ramp-up sequence. When the RAM
segment final address value for Profile 2 is reached, the
sequence is over and the composite sweep has completed.
Issuing another I/O update restarts the burst process.
A continuous internal profile control mode is one in which the
composite sweep is continuously executed for as long as the
device is programmed into that mode. Using the previous
example, except programming the CFR1<29:27> bits to
Logic 101(b), the operation would be identical until the RAM
segment final address value for Profile 2 is reached. At this
point, instead of stopping the sequence, the device jumps back
to the beginning address of Profile 0 and continues sweeping.
Linear Sweep Mode
The AD9954 is placed in linear sweep mode using the Linear
Sweep Enable Bit CR1<21>. PS1 must be tied low. When in
linear sweep mode, the AD9954 output frequency ramps up
from a starting frequency, programmed by FTW0 to a finishing
frequency FTW1, or down from FTW1 to FTW0. The delta
frequency tuning words and the ramp rate word determine the
rate of this ramping. The Linear Sweep No-Dwell Bit CFR1<2>
controls the behavior of the device upon reaching the final
frequency.
When PS0 is high, the 32-bit rising delta frequency tuning word
(RDFTW) is the seed value for the frequency accumulator, it
Mode Description
Internal control inactive
Internal control active, single-burst, activate
Profile 0, then Profile 1, then stop
Internal control active, single-burst, activate
Profile 0, then Profile 1, then Profile 2, then stop
Internal control active, single-burst, activate
Profile 0, then Profile 1, then Profile 2, then
Profile 3, then stop
Internal control active, continuous, activate
Profile 0, then Profile 1, then Loop Starting 0
Internal control active, continuous, activate
Profile 0, then Profile 1, then Profile 2, then
Loop Starting 0
Internal control active, continuous, activate
Profile 0, then Profile 1, then Profile 2, then
Profile 3, and then Loop Starting 0
Invalid
Rev. B | Page 18 of 40
ramps from FTW0 to FTW1 and the RSRR register is loaded
into the sweep rate timer. When the timer counts down to one,
the frequency accumulator cycles once, increasing by the seed
value. This accumulation of the RDFTW at the rate given by the
ramp rate (RSRR) continues until the output of the frequency
adder is equal to the FTW1 register value, or PS0 is pulled low.
When PS0 is low, the 32-bit falling delta frequency tuning word
(FDFTW) is the seed value for the frequency accumulator, it
ramps down from FTW1 to FTW0 and the FSRR register is
loaded into the sweep rate timer. When the timer counts down
to one, the frequency accumulator cycles once, decreasing by
the seed value. This accumulation of the FDFTW at the rate
given by the ramp rate (FSRR) continues until the output of the
frequency adder is equal to the FTW0 register value, or PS0 is
pulled high.
Pin PS0 controls the direction of the sweep, rising to FTW1 or
falling to FTW0. Upon reaching the destination frequency, the
AD9954 linear sweep function either holds at the destination
frequency until the state on PS0 is changed or immediately
returns to the initial frequency, FTW0, depending on the state
of the Linear Sweep No-Dwell Bit CFR1<02>. While operating
in linear sweep mode, toggling PS0 does not cause the device to
generate an internal I/O update. When PS0 is acting as the
sweep direction indicator, any transfer of data from the I/O
buffers to the internal registers can only be initiated by a rising
edge on the I/O UPDATE pin.
The linear sweep function of the AD9954 requires the lowest
frequency to be loaded into the FTW0 register and the highest
frequency into the FTW1 register. For piece-wise, nonlinear
frequency transitions, it is necessary to reprogram the registers
while the frequency transition is in process.
After a reset, the device is initially in single-tone mode. The
programming steps to operate in linear sweep mode are:
0)
1)
2)
3)
4)
5)
Figure 21 depicts a typical frequency ramping operation. The
device initially powers up in single-tone mode. The profile
inputs are low, setting FTW0 as the seed value for the phase
accumulator. The user then writes to the linear sweep enable bit,
the rising and falling delta frequency tuning words, and ramp
rates via the serial port (Point A in Figure 21. In this example, the
linear sweep no-dwell bit is cleared (CFR1<2>).
PS1:0 = 00.
Set the linear sweep enable bit (CFR1<21>) and set or clear
the linear sweep no-dwell bit (CFR1<2>) as desired.
Program the rising and falling delta frequency tuning
words and ramp rate values.
Program the lower and higher output frequencies into the
FTW0 and FTW1 registers, respectively.
Apply an I/O update to move this data into the registers
(the instantaneous output frequency is FTW0).
Change the PS0 input as desired to sweep between the
lower to higher frequency and back.