EVM6435BHF Semtech, EVM6435BHF Datasheet
EVM6435BHF
Specifications of EVM6435BHF
Related parts for EVM6435BHF
EVM6435BHF Summary of contents
Page 1
... DAC Programming per Channel or Set of Channels • Readback of DAC Input Data and Output Value • Small 100-Pin MQFP Package • Low-Cost, Highly Integrated Multi-DAC Solution Applications • Automated Test Equipment (ATE) • Cost Sensitive applications requiring multiple programmable voltage and currents 1 Companion DAC www.semtech.com ...
Page 2
... TEST AND MEASUREMENT PRODUCTS Functional Block Diagram TESTMODE SHIFTOUT* 2006 Semtech Corp. / Rev. 3, 8/25/06 SDIN CLKIN DAC 0 DACEN UPDATE STORE LOAD RANK RESET* DAC 39 SDOUT LDOUT DACOUT 2 Edge6435/6436 Channel 0 4 VOUTA 2 VOUTB 2 VOUTC 2 IOUTC 2 IOUTD Channel 1 4 VOUTA 2 VOUTB 2 VOUTC 2 IOUTC ...
Page 3
... TEST AND MEASUREMENT PRODUCTS PIN Description 2006 Semtech Corp. / Rev. 3, 8/25/ Edge6435/6436 " " " " www.semtech.com ...
Page 4
... TEST AND MEASUREMENT PRODUCTS PIN Description (continued 2006 Semtech Corp. / Rev. 3, 8/25/ Edge6435/6436 . www.semtech.com ...
Page 5
... TEST AND MEASUREMENT PRODUCTS PIN Description (continued 2006 Semtech Corp. / Rev. 3, 8/25/ Edge6435/6436 www.semtech.com d ...
Page 6
... SHIFTOUT* 9 UPDATE 10 STORE 11 FORMAT 12 SDIN 13 LD_OUT 14 CLKIN 15 LOAD 16 TEST_MODE 17 SDOUT 18 IOUTD_0 19 IOUTD_1 20 AGND 21 AVDD 22 AVEE 23 R_OFFSET_B 24 R_VGAIN_B 25 AGND 26 AVDD 27 AVEE 28 AVEE 29 AVCC 30 VOUTB_0 2006 Semtech Corp. / Rev. 3, 8/25/06 Edge6435/6436 VOUTA_13 VOUTA_14 VOUTA_15 AVEE AVCC AGND AVDD AVEE R_OFFSET_A R_VGAIN_A R_MASTER VREF ...
Page 7
... Voltage Output Overview", "DAC Current Output Overview", and specifications for details. Note 2: Group C has both voltage and current outputs. 2006 Semtech Corp. / Rev. 3, 8/25/06 Grouping of DACs DACs are separated into channels of 4 distinct functional groups. Groups are defined by: – ...
Page 8
... As can be seen from Equation 1, the accuracy of the DAC output voltage after calibration is dependent upon the temperature coefficients of V and the external resistors. REF 2006 Semtech Corp. / Rev. 3, 8/25/06 Minimum / Maximum Output Voltages See Table 2 for the minimum and maximum possible DAC is a OUT ...
Page 9
... I is the output current of the Group D DAC OUT_D externally applied 2.5V reference voltage REF 2006 Semtech Corp. / Rev. 3, 8/25/06 Edge6435/6436 R_IGAIN_D is the value of an external resistor that sets the output current range for Group D DACs (78.12K R_IGAIN_D 156.25K ) DATA is the base-10 value of the binary code loaded into the DAC shift register (see Figures 4 and 5) ...
Page 10
... Edge6435/6436 compute the input to DAC’s Latch A (of Rank A). There needs least one clock edge after LOAD is set to logic “low” before STORE is set to logic “high” (see Figure 21). 2006 Semtech Corp. / Rev. 3, 8/25/06 Edge6435/6436 UPDATE Following the STORE of multiple DAC values into Rank A ...
Page 11
... Figure 7 shows details of programming a channel’s Set Register, which is stored in the Edge6435/6436 by the STORE input. A channel may 2006 Semtech Corp. / Rev. 3, 8/25/06 Edge6435/6436 belong to none, one, or any combination distinct sets. The address maps show that a channel’s DAC (or ...
Page 12
... ADDRESS AND SET DECODERS FORMAT DISABLE LOAD CLKIN SDIN S RESET* Programming Logic NOTE: Not shown is the function of the Latched Data Readback (via LDOUT) and the DAC Value Readback (via DACOUT). 2006 Semtech Corp. / Rev. 3, 8/25/06 STORE UPDATE UPDATEA D D UPDATEA D7-D0 D ...
Page 13
... DAC allow the DAC to be shared in a system). NOTE: CALSEL common to all DACs assigned to a Channel DAC Output (CODE 4096) CODE = + O 4096 Figure 2. Details of DAC Data Latches for 13 Bit DACs (Groups A, B, and C) 2006 Semtech Corp. / Rev. 3, 8/25/06 UPDATEA SEQUENCE GENERATOR ...
Page 14
... TEST AND MEASUREMENT PRODUCTS Circuit Description (continued) D[12:7] STORE SR0 DACSEL SR1 SR2 SR3 D[8:7] SR4 KEY: VA, VB, VC, VD: VS: Figure 3. Details of DAC Data Latches for 6 Bit DACs (Group D) 2006 Semtech Corp. / Rev. 3, 8/25/ Value Latches Value Selection Latch 14 Edge6435/6436 UPDATEB RANK ...
Page 15
... Figure 4. Format of Address and Data in Shift Register (4 Channel Format D12 D11 D10 D9 MSB REGISTER Figure 5. Format of Address and Data in Shift Register (8 Channel Format) LSB Addr. SDIN CLKIN LOAD SDOUT Figure 6. Serial Data Programming Sequence 2006 Semtech Corp. / Rev. 3, 8/25/06 DATA DATA ...
Page 16
... Figure 8. Format of Address and Data for Programming to SET REGISTER (8 Channel Format MSB REGISTER Figure 9. Format of Address and Data for Programming a Channel’s Function (4 Channel Format MSB REGISTER Figure 10. Format of Address and Data for Programming a Channel’s Function (8 Channel Format) 2006 Semtech Corp. / Rev. 3, 8/25/06 DATA DATA ...
Page 17
... R1 R0 D12 D11 D10 D9 MSB If Set 4 is selected, then channel’s DAC value or Function will be ‘stored’. If Set 3 is selected, then the channel will not be ‘addressed’. Figure 11. Example of Channel’s Set Selection (4 Channel Format) 2006 Semtech Corp. / Rev. 3, 8/25/06 DATA ...
Page 18
... Configure Group C DACs as Vout Configure Group C DACs as Iout Reserved Note 1: All 6-bit DACs are programmed with the MSB at the D12 bit position and extending down to D7 for the LSB. D[6:0] bit positions are “don’t cares”. 2006 Semtech Corp. / Rev. 3, 8/25/ ...
Page 19
... PS2, PS1, PS0 bits (PS0 is LSB). Parallel Load of denoted IOUTD DACs assigned to the PINCAST "Set" addressed using the PS2, PS1, PS0 bits (PS0 is LSB). Reserved Table 3. Address Map (4 Channel Format) – cont’d 2006 Semtech Corp. / Rev. 3, 8/25/ 0x10 0000 0x01 0000 ...
Page 20
... Configure Group C DAC as Vout Configure Group C DAC as Iout Note 1: All 6-bit DACs are programmed with the MSB at the D12 bit position and extending down to D7 for the LSB. D[6:0] bit positions are “don’t cares”. 2006 Semtech Corp. / Rev. 3, 8/25/ ...
Page 21
... Note 1: All 6-bit DACs are programmed with the MSB at the D12 bit position and extending down to D7 for the LSB. D[6:0] bit positions are “don’t cares”. Table 4. Address Map (8 Channel Format) – cont’d 2006 Semtech Corp. / Rev. 3, 8/25/ ...
Page 22
... PS2, PS1, PS0 bits (PS0 is LSB). Parallel Load of denoted IOUTD DACs assigned to the PINCAST "Set" addressed using the PS2, PS1, PS0 bits (PS0 is LSB). Table 4. Address Map (8 Channel Format) – cont’d 2006 Semtech Corp. / Rev. 3, 8/25/ 0x10 0000 0x01 0000 ...
Page 23
... TEST_MODE Address Decoder DAC_OUT Figure 12. DAC Voltage Output via DAC_OUT 2006 Semtech Corp. / Rev. 3, 8/25/06 DAC Value Readback via DAC_OUT Voltage Outputs Each voltage output of the Edge6435/6436 has high impedance FET(s) connected from the outputs to a common analog line, DAC_OUT, that provides readback of each DAC’ ...
Page 24
... DECODER DAC_OUT NOTE: WHEN ADDRESS 64 IS INVOKED (PARALLEL LOAD), SCAN IS DISABLED. Figure 13. DAC Current Output vs DAC_OUT 2006 Semtech Corp. / Rev. 3, 8/25/06 The typical "ON" resistance of the FET switch but can vary from 900 function of process and output voltage. Notes when Using DAC_OUT Feature with ...
Page 25
... TESTMODE 13 DACSEL Figure 14. Latched Data Readback Functional Block Diagram 2006 Semtech Corp. / Rev. 3, 8/25/06 A DACs Rank A or Rank B latches are selcted by the RANK input for subsequent readback. Readback is enabled internally by TESTMODE high whereupon the selected DAC’s Rank A or Rank B latch outputs are loaded into the READBACK REGISTER by a leading edge of CLKIN while SHIFTOUT* is high ...
Page 26
... GND The Selection of R_MASTER Establishes I REF NOTE: Pull-down resistors required on RANK, DACEN, and RESET* to ensure they are NOTE: Power Supply inputs AVCC, AVDD, DVDD and AVEE need bypass capacitors 2006 Semtech Corp. / Rev. 3, 8/25/06 +5V 0V –5V +3.3V DVDD AGND ...
Page 27
... The E6435/E6436 can be configured to provide all of the DAC levels required for 4 fully-featured high-speed pin channels or 8 fully-featured low-speed pin channels when used with other Semtech pin electronics components. Since each E6435/E6436 DAC channel includes 2 sets of calibration registers, DAC channels can be shared across two distinct functions in an application to minimize the overall number of level DACs required in a system ...
Page 28
... E7804 devices and are shared with the lower voltage clamp threshold on the E42X7. Table 6. E6435/E6436 Per-Channel DAC Connectivity for Low-Speed Pin Driver, Comparator, Continuity Test Circuit, and Per-Pin PMU Solution 2006 Semtech Corp. / Rev. 3, 8/25/06 E6435/ E6436 ...
Page 29
... Use variation GB-1 for lead form options and BB for body dime. 8. Use variation GC-1 for lead form options and BB for body dime. 9. Use MS-022 variation BB for body dimensions. 10. N.J.R. means no single JEDEC reference putline or standard. 2006 Semtech Corp. / Rev. 3, 8/25/06 .30 RAD. TYP . –B– A .25 .17 MAX B ...
Page 30
... TEST AND MEASUREMENT PRODUCTS Recommended Operating Conditions NOTE: All supplies are referenced to AGND unless otherwise noted. 2006 Semtech Corp. / Rev. 3, 8/25/ – – – – Edge6435/6436 – – ˚ ˚ ˚ ˚ ˚ www.semtech.com ...
Page 31
... Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these, or any other conditions beyond those listed, is not implied. Exposure to absolute maximum conditions for extended periods may affect device reliability. 2006 Semtech Corp. / Rev. 3, 8/25/ ...
Page 32
... TEST AND MEASUREMENT PRODUCTS DC Characteristics < 2006 Semtech Corp. / Rev. 3, 8/25/ Edge6435/6436 – – – – – – – – – – – – – – – – www.semtech.com µ µ µ V ˚ µ V ˚ ...
Page 33
... TEST AND MEASUREMENT PRODUCTS DC Characteristics (continued 2006 Semtech Corp. / Rev. 3, 8/25/ – – – Edge6435/6436 – – – – – – – – – – – – www.semtech.com µ A µ ˚ ˚ µ µ A µ ˚ ˚ µ A ...
Page 34
... Range error and offset error are due to E6435/6436 only. External resistor tolerances and VREF tolerance not included. Figure 17. Representation of DAC Offset Error and Range Error Measured DAC Output at 20% of Max Code Figure 18. Representation of 2-Point DAC Integral Non-Linearity (INL) 2006 Semtech Corp. / Rev. 3, 8/25/06 DAC Output (Voltage or Current) Maximum Range Real Transfer Characteristic is somewhere between "dotted" lines ...
Page 35
... Figure 20. Representation of Differential Non-Linearity (DNL) 2006 Semtech Corp. / Rev. 3, 8/25/06 DAC Output (Voltage or Current) Maximum Measured DAC output at Max Code Range DAC Integral Non-Linearity (INL) Min Code Max Code Minimum Range 35 Edge6435/6436 DAC Code Measured DAC output must not change by more than ...
Page 36
... TEST AND MEASUREMENT PRODUCTS DC Characteristics (continued) Power Supplies < Note 1: CLKIN Low, quiescent 2006 Semtech Corp. / Rev. 3, 8/25/ – – – – – 2 – 2 – 1 – – – – 1 – – – 1 – Edge6435/6436 µ µ µ www.semtech.com ...
Page 37
... TEST AND MEASUREMENT PRODUCTS AC Characteristics ± ± ± ± 2006 Semtech Corp. / Rev. 3, 8/25/ Edge6435/6436 µ s µ s µ s µ s µ s µ s µ s µ s µ s µ s µ µ s µ µ s www.semtech.com ...
Page 38
... DAC output to change from positive full-scale to 0.5V. Note 6: Current DAC Output Disable Time is measured from the falling edge of DACEN as the amount of time required for the DAC output to change by 10%. Figure 21. Individual DAC Storing and DAC Updating (RESET* high) 2006 Semtech Corp. / Rev. 3, 8/25/06 3C 16C Valid Data SDIN ...
Page 39
... TEST AND MEASUREMENT PRODUCTS AC Characteristics (continued) 2006 Semtech Corp. / Rev. 3, 8/25/06 Figure 23. RESET* and DACEN Timing STORE or UPDATE 1 C RANK, > TESTMODE LOAD 1 C CLKIN TSU_SOUT THLD_SOUT SHIFTOUT* TO_LDOUT LDOUT Figure 24. SHIFTOUT*, LDOUT Timing 39 Edge6435/6436 TSU_SOUT D1 D0 www.semtech.com ...
Page 40
... TEST AND MEASUREMENT PRODUCTS Ordering Information M Contact Information 10021 Willow Creek Rd., San Diego, CA 92131 Phone: (858)695-1808 FAX (858)695-2633 2006 Semtech Corp. / Rev. 3, 8/25/ This product is lead-free. Semtech Corporation Test and Measurement Division 40 Edge6435/6436 www.semtech.com ...