DS99R103TVSX National Semiconductor, DS99R103TVSX Datasheet - Page 14
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DS99R103TVSX
Manufacturer Part Number
DS99R103TVSX
Description
Manufacturer
National Semiconductor
Datasheet
1.DS99R103TVSX.pdf
(24 pages)
Specifications of DS99R103TVSX
Number Of Elements
1
Input Type
CMOS/TTL
Operating Supply Voltage (typ)
3.3V
Output Type
Serializer
Differential Output Voltage
1.2V
Transmission Data Rate
960Mbps
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Number Of Receivers
24
Number Of Drivers
1
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DS99R103TVSX/NOPB
Manufacturer:
Texas Instruments
Quantity:
10 000
www.national.com
LVCMOS PARALLEL INTERFACE PINS
25-28,
31-34
13-16,
21-24
3-6,
9-12
18
CONTROL AND CONFIGURATION PINS
43
48
1
17
2
LVDS SERIAL INTERFACE PINS
41
42
POWER / GROUND PINS
39
40
47
46
45
44
37
38
36
35
30
29
20
19
7
8
Pin #
DS99R104 Deserializer Pin Descriptions
ROUT[7:0]
ROUT[15:8]
ROUT[23:16] LVCMOS_O
RCLK
RRFB
REN
RPWDNB
LOCK
RESRVD
RIN+
RIN−
VDDIR
VSSIR
VDDPR0
VSSPR0
VDDPR1
VSSPR1
VDDR1
VSSR1
VDDR0
VSSR0
VDDOR1
VSSOR1
VDDOR2
VSSOR2
VDDOR3
VSSOR3
Pin Name
LVCMOS_O
LVCMOS_O
LVCMOS_O
LVCMOS_I
LVCMOS_I
LVCMOS_I
LVCMOS_O
LVCMOS_I
LVDS_I
LVDS_I
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
I/O
Receiver Parallel Interface Data Outputs – Group 1
Receiver Parallel Interface Data Outputs – Group 2
Receiver Parallel Interface Data Outputs – Group 3
Parallel Interface Clock Output Pin. Strobe edge set by RRFB configuration pin.
Receiver Clock Edge Select Pin
RRFB = H; ROUT LVCMOS Outputs strobed on the Rising Clock Edge.
RRFB = L; ROUT LVCMOS Outputs strobed on the Falling Clock Edge.
Receiver Data Enable
REN = H; ROUT[23-0] and RCLK are Enabled (ON).
REN = L; ROUT[23-0] and RCLK are Disabled (OFF), Receiver ROUT[23-0] and RCLK Outputs
are in TRI-STATE, PLL still operational and locked to TCLK.
Receiver Data Enable
REN = H; ROUT[23-0] and RCLK are Enabled (ON).
REN = L; ROUT[23-0] and RCLK are Disabled (OFF), Receiver ROUT[23-0] and RCLK Outputs
are in TRI-STATE, PLL still operational and locked to TCLK.
LOCK indicates the status of the receiver PLL
LOCK = H; receiver PLL is locked
LOCK = L; receiver PLL is unlocked, ROUT[23-0] and RCLK are TRI-STATED
RESERVED – This pin MUST be tied LOW.
Receiver LVDS True (+) Input This input is intended to be terminated with a 100 ohm load to
the RIN+ pin. The interconnect should be AC Coupled to this pin with a 100 nF capacitor.
Receiver LVDS Inverted (−) Input This input is intended to be terminated with a 100 ohm load
to the RIN- pin. The interconnect should be AC Coupled to this pin with a 100 nF capacitor.
Analog LVDS Voltage supply, Power
Analog LVDS Ground
Analog Voltage supply, PLL Power
Analog Ground, PLL Ground
Analog Voltage supply, PLL VCO Power
Analog Ground, PLL VCO Ground
Digital Voltage supply, Logic Power
Digital Ground, Logic Ground
Digital Voltage supply, Logic Power
Digital Ground, Logic Ground
Digital Voltage supply, LVCMOS Output Power
Digital Ground, LVCMOS Output Ground
Digital Voltage supply, LVCMOS Output Power
Digital Ground, LVCMOS Output Ground
Digital Voltage supply, LVCMOS Output Power
Digital Ground, LVCMOS Output Ground
14
Description