MT9171AN1 Zarlink, MT9171AN1 Datasheet - Page 3

• Manufacturer Part Number: MT9171AN1
• Description: Digital Subscriber Interface Circuit 24-Pin SSOP Tube
• Manufacturer: Zarlink

Specifications of MT9171AN1

• Package: 24SSOP
• Maximum Data Rate: 160 Kbps
• Transmission Media Type: Twisted Pair
• Power Supply Type: Analog
• Typical Supply Current: 10 mA
• Typical Operating Supply Voltage: 5 V
• Minimum Operating Supply Voltage: 4.75 V
• Maximum Operating Supply Voltage: 5.25 V

Pin Description (continued)
22
10
12
13
14
15
16
17
18
19
20
21
22
11
9
Pin #
24
10
12
13
14
15
16
17
19
20
18
21
22
23
24
11
8,
1,6,
18,
20,
11,
28
12
13
14
15
16
17
19
21
22
23
25
24
26
27
28
DSTo/Do Data ST-BUS Out/Data Out (Digital). A 2.048 Mbit/s serial PCM/data output in
F0o/RCK Frame Pulse Out/Receive Bit Rate Clock output (Digital). In DN mode a 244 ns
L
C4/TCK
CDSTo/
DSTi/Di
CDSTi/
Precan
OUT
OSC2
OSC1
TEST
Name
CDo
CDi
V
V
NC
L
DD
SS
IN
DIS L
Control/Data ST-BUS In/Control/Data In (Digital). A 2.048 Mbit/s serial control
& signalling input in DN mode. In MOD mode this is a continuous bit stream at
the bit rate selected.
Control/Data ST-BUS Out/Control/Data Out (Digital). A 2.048 Mbit/s serial
control & signalling output in DN mode. In MOD mode this is a continuous bit
stream at the bit rate selected.
Negative Power Supply (0 V).
DN mode. In MOD mode this is a continuous bit stream at the bit rate selected.
Data ST-BUS In/Data In (Digital). A 2.048 Mbit/s serial PCM/data input in DN
mode. In MOD mode this is a continuous bit stream at the bit rate selected.
wide negative pulse indicating the end of the active channel times of the device
to allow daisy chaining. In MOD mode provides the receive bit rate clock to the
system.
Data Clock/Transmit Baud Rate Clock (Digital). A 4.096 MHz TTL compatible
clock input for the MASTER and output for the SLAVE in DN mode. For MOD
mode this pin provides the transmit bit rate clock to the system.
Oscillator Output. CMOS Output.
Oscillator Input. CMOS Input. D.C. couple signals to this pin. Refer to D.C.
Electrical Characteristics for OSC1 input requirements.
Precanceller Disable. When held to Logic ’1
precanceller is forced to V
logic ’0’, the L
internal pulldown (50 kΩ) is provided on this pin.
No Connection. Leave open circuit
logic “0”, L
this pin.
Test Pin.
Receive Signal input (Analog).
Positive Power Supply (+5 V) input.
OUT
Disable. When held to logic “1”, L
OUT
Connect to V
Zarlink Semiconductor Inc.
OUT
functions normally. An internal pulldown (50 kΩ) is provided on
MT9171/72
to the precanceller path is enabled and functions normally. An
3
SS
Bias
.
thus bypassing the precanceller section. When
Description
OUT
is disabled (i.e., output = V
’,
the internal path from L
Data Sheet
Bias
OUT
). When
to the