ML571-1982CLK National Semiconductor, ML571-1982CLK Datasheet - Page 17

• Manufacturer Part Number: ML571-1982CLK
• Manufacturer: National Semiconductor

Specifications of ML571-1982CLK

• Lead Free Status / RoHS Status: Supplier Unconfirmed

5.2 Programming The Output Format Timing
When PLL 1 is stable and locked to the input reference, the
output format timing should be specified. The functional block
HD_CLK (MHz)
74.25/1.001
148.5/1.001
74.25
148.5
TABLE 5. HD Clock Frequency Selection
Register 08h
HD_FREQ
0h
1h
2h
3h
PLL#
2
3
2
3
17
diagram for TOF generation and output initialization is shown
in Figure 3.
For proper output generation and initialization, the reference
format and output format timings must be fully and correctly
programmed to the output format registers 09h–12h, which
specify the following:
•
•
•
•
•
Output TOF Clock
Output Frame Timing
Reference Frame Timing
Input-Output Frame Rate Ratio
Output Frame Line Offset
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