AD9380/PCBZ Analog Devices Inc, AD9380/PCBZ Datasheet - Page 22

• Manufacturer Part Number: AD9380/PCBZ
• Manufacturer: Analog Devices Inc

Specifications of AD9380/PCBZ

• Lead Free Status / RoHS Status: Supplier Unconfirmed

AD9380
This information is the fundamental difference between DVI
and HDMI transmissions and is located in read-only registers
R0x5A to R0xEE. In addition to this information, registers are
provided to indicate that new information has been received.
Registers with addresses ending in 0xX7 or 0xXF, beginning at
R0x87 contain the new data flag (NDF) information. These
registers contain the same information and all are reset once
any of them are read. Although there is no external interrupt
signal, the user easily can read any of these registers to see if
there is new information to be processed.
Table 11.
Port
Bit
4:4:4
4:2:2
4:4:4 DDR
4:2:2 to 12
1
Arrows in the table indicate clock edge. Rising edge of clock = ↑, falling edge = ↓.
Red
7
Red/Cr [7:0]
CbCr [7:0]
DDR
DDR
CbCR [11:0]
CB/CROUT
DATAOUT
↑
↓
DATACK
6
DATACK
DATAIN
DATAIN
HSOUT
HSOUT
G [3:0]
R [7:0]
YOUT
HSIN
HSIN
5
1
1
NOTES:
1. PIXEL AFTER HSOUT CORRESPONDS TO BLUE INPUT.
2. EVEN NUMBER OF PIXEL DELAYS BETWEEN HSOUT AND DATAOUT.
4
P0
P0
3
DDR
P1
P1
↑
2
B [7:4]
P2
P2
2 CLOCK CYCLE DELAYS
2 CLOCK CYCLE DELAYS
1
0
P3
P3
Figure 16. YCrCb ADC Timing
Figure 15. RGB ADC Timing
Green
7
Green/Y [7:0]
Y [7:0]
DDR
DDR
P4
Rev. 0 | Page 22 of 60
P4
↑
↓
6
B [3:0]
G [7:4]
P5
P5
5
P6
P6
TIMING DIAGRAMS
Figure 15 and Figure 16 show the operation of the AD9380.The
output data clock signal is created so that its rising edge always
occurs between data transitions and can be used to latch the
output data externally. There is a pipeline in the AD9380 that
must be flushed before valid data becomes available. This
means six data sets are presented before valid data is available.
4
P7
P7
DDR 4:2:2
DDR 4:2:2
Y [11:0]
3
P8
8 CLOCK CYCLE DELAYS
P8
8 CLOCK CYCLE DELAYS
P0
Y0
B0
2
↑
↓
CbCr [11:0]
Y,Y [11:0]
P9
P9
P1
1
Y1
R0
P10
P10
0
P2
Y2
B2
P11
P11
Blue
7
Blue/Cb [7:0]
DDR 4:2:2
P3
Y3
R2
6
5
↑
CbCr
4
3
↓
Y, Y
2
1
0