A2550KLP-T Allegro Microsystems Inc, A2550KLP-T Datasheet - Page 7

• Manufacturer Part Number: A2550KLP-T
• Manufacturer: Allegro Microsystems Inc

Specifications of A2550KLP-T

• Lead Free Status / RoHS Status: Compliant

A2550
Pin Descriptions
EN Enable pin; logical OR with ENBAT. This logic-level
input enables the A2550. If there are no faults, the regulator
is live and outputs can be switched. When both the EN and
ENBAT pins are held low, the A2550 enters Sleep mode.
ENBAT Enable pin; logical OR with EN. Same as EN,
except that this pin is high-voltage protected, and specified
up to V
Not to exceed V
between the ENBAT and VBB pins.
WDI Watchdog Input. Monitors the microcontroller to detect
when it stops functioning. This pin is connected to an edge
trigger. To avoid a fault, the latter must be triggered before
CWD times-out. When not used, WDI is defeated by tying it
to NPOR and shorting CWD.
CWD Watchdog timer capacitor terminal. Used with WDI.
A current source charges the external capacitor tied to this
pin. A reverse current source discharges the capacitor when
either WDI transitions or the high Trip Voltage, V
reached (see specification table for values). The charge-up
time defines the maximum period allowed WDI to toggle
before a fault is issued; the charge-down time defines the
width of NPOR pulses issued to wake-up the microcon-
troller.
NPOR NOT Power On Reset. This active-low pin indicates
a fault. Except for watchdog faults, NPOR is held low during
the fault state. Refer to the Fault Logic table to determine
BB
so it can be tied to the battery or power source.
BB
because the ESD structure places a diode
Functional Description
TRIP(H)
, is
which faults are latched. Watchdog faults generate a train of
pulses to “wake up” the microcontroller.
CPOR Power-On Reset timer capacitor terminal. When-
ever VREG5 first charges up (at start-up or when a fault
is cleared) a “fault” condition remains in effect until the
onboard current source drives CPOR to the high Trip Volt-
age, V
controller, to be initialized before activating the outputs.
CPOR is defeated by pulling it high to VREG5 with a 50 k
resistor.
INx Input pin. Active-high CMOS input. Internally tied to
200 k pull-down resistors.
OUTx Output pin. Open drain DMOS. Clamps to a voltage
greater than V
Includes current mirror for overcurrent protection.
VBB Power pin, or “battery.” Specified for automotive volt-
ages.
VREG5 5 V Regulator output. Clamped at the Current
Limit Level (
decreases, VREG5 is pulled below the UVLO level. In that
case, a fault is generated (NPOR low).
LGND Logic Ground. The reference pin for the logic
circuits. Must be connected to PGND externally.
PGND Power Ground. The reference pin for the outputs
(OUTx). Must be connected to LGND externally.
Relay Driver with 5 V Regulator
TRIP(H)
for Automotive Applications
I
. This allows external circuits, such as a micro-
REG5Lim
BB
when an inductive load is switched off.
) for excessive loads. As load resistance
115 Northeast Cutoff
1.508.853.5000; www.allegromicro.com
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 U.S.A.
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