CY2SSTU32864BVXI Cypress Semiconductor Corp, CY2SSTU32864BVXI Datasheet

CY2SSTU32864BVXI

Manufacturer Part Number

CY2SSTU32864BVXI

Description

Manufacturer

Cypress Semiconductor Corp

Datasheet

1.CY2SSTU32864BVXI.pdf (9 pages)

Specifications of CY2SSTU32864BVXI

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Cypress Semiconductor Corporation

Document #: 38-07576 Rev. *A

Features

Functional Description

All clock and data inputs are compatible with the JEDEC

standard for SSTL_18. The control inputs are LVCMOS. All

outputs are 1.8-V CMOS drivers that have been optimized to

drive the DDR-II DIMM load. The CY2SSTU32864 operates

from a differential clock (CK and CK#). Data are registered at

the crossing of CK going high, and CK# going low.

The C0 input controls the pinout configuration of the 1:2 pinout

from A configuration (when low) to B configuration (when

high). The C1 input controls the pinout configuration from

25-bit 1:1 (when low) to 14-bit 1:2 (when high). C0 = 1 and

C1 = 0 is not allowed and either it does or it doesn’t defaults to

the C0 = C1 = 0 state.

• Operating frequency: DC to 500 MHz

• Supports DDRII SDRAM

• Two operations modes: 25 bit (1:1) and 14 bit (1:2)

• 1.8V operation

• Fully JEDEC-compliant

• 96-ball VFBGA

Block Diagram

•

3901 North First Street

PRELIMINARY

JEDEC-Compliant Data Register

1.8V, 25-bit (1:1) or 14-bit (1:2)

The device monitors both DCS# and CSR# inputs and will gate

the Qn outputs from changing states when both DCS# and

CSR# inputs are high. If either DCS# or CSR# input is low, the

Qn outputs will function normally. The RESET input has priority

over the DCS# and CSR# control and will force the outputs

low. If the DCS#-control functionality is not desired, the CSR#

input can be hardwired to ground, in which case the set-up

time requirement for DCS# would be the same as for the other

D data inputs.

The device supports low-power standby operation. When the

reset input (RESET#) is low, the differential input receivers are

disabled, and undriven (floating) data, clock, and reference

voltage (VREF) inputs are allowed. In addition, when RESET#

is low, all registers are reset and all outputs are forced low. The

LVCMOS RESET# and Cn inputs must always be held at a

valid logic high or low level. To ensure defined outputs from the

must be held in the low state during power-up.

In the DDR-II RDIMM application, RESET# is specified to be

completely asynchronous with respect to CK and CK#.

Therefore, no timing relationship can be guaranteed between

the two. When entering reset, the register will be cleared and

the outputs will be driven low quickly, relative to the time to

disable the differential input receivers. However, when coming

out of reset, the register will become active quickly, relative to

the time to enable the differential input receivers.

Pin Configuration

•

San Jose

CA 95134

CY2SSTU32864

Revised May 4, 2004

•

408-943-2600

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CY2SSTU32864BVXI Summary of contents

Page 1

... The C1 input controls the pinout configuration from 25-bit 1:1 (when low) to 14-bit 1:2 (when high and not allowed and either it does or it doesn’t defaults to the state. Block Diagram Cypress Semiconductor Corporation Document #: 38-07576 Rev. *A PRELIMINARY 1.8V, 25-bit (1:1) or 14-bit (1:2) JEDEC-Compliant Data Register ...

Page 2

Pin Definition Pin Number Pin Name (C0=0, C1=0) GND B3, B4, D3, D4, F3, F4, H3, H4, K3, K4, M3, M4, P3, P4 VDD A4, C3, C4, E3, E4, G3, G4, J3, J4, L3, L4, N3, N4, R3, R4, T4 ...

Page 3

Pin Definition (Continued) Q12A, Q13A P5, R5 Q14A T5 Q1B Q2B-3B Q4B Q5B, 6B, 8B, 9B, 10B, Q11B Q12B, 13B Q14B Q15-25 B6, C6, E6, F6, K6, L6, M6, N6, P6, R6, T6 QCSA# H5 QCSB# QODTA D5 QODTB QCKEA ...

Page 4

Recommended Operating Conditions Parameter Description T (Ind.) Ambient Operating Temp A T (Com.) Ambient Operating Temp A V Operating Voltage DD Absolute Maximum Conditions Parameter Description [2,3] V Input Voltage Range IN V Output Voltage Range OUT T Storage Temperature ...

Page 5

DC Electrical Specifications Parameter Description V Input Voltage I I Input Current Input Low Voltage IL DC Input Low Voltage V AC Input High Voltage IH DC Input High Voltage V Output Low Voltage OL V Output ...

Page 6

Figure 2. Voltage and Current Inputs Active and Inactive Times Document #: 38-07576 Rev. *A PRELIMINARY Figure 1. Test Load for Timing Measurements #1 Figure 3. Pulse Duration CY2SSTU32864 Page ...

Page 7

Document #: 38-07576 Rev. *A PRELIMINARY Figure 4. Set up and Hold Times Figure 5. Propagation Delay Figure 6. Propagation Delay after RESET# CY2SSTU32864 Page ...

Page 8

... Ordering Information Part Number CY2SSTU32864BVXC CY2SSTU32864BVXCT CY2SSTU32864BVXI CY2SSTU32864BVXIT Package Drawing and Dimensions TOP VIEW A1 CORNER 5.50±0.10 SEATING PLANE C Document #: 38-07576 Rev. *A © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product ...

Page 9

Document History Page Document Title: CY2SSTU32864 1.8V, 25-bit (1:1) or 14-bit (1:2) JEDEC-Compliant Data Register Document #: 38-07576 Rev. *A Issue Rev. ECN No. Date ** 129199 09/09/03 *A 224102 See ECN Document #: 38-07576 Rev. *A PRELIMINARY Orig. of ...

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