MC100LVEL90DWR2 ON Semiconductor, MC100LVEL90DWR2 Datasheet

MC100LVEL90DWR2

Manufacturer Part Number

MC100LVEL90DWR2

Description

Manufacturer

ON Semiconductor

Datasheet

1.MC100LVEL90DWR2.pdf (6 pages)

Specifications of MC100LVEL90DWR2

Logic Family

ECL

Logical Function

Translator

Technology

ECL

High Level Output Current

-50mA

Low Level Output Current

50mA

Abs. Propagation Delay Time

710ps

Mounting

Surface Mount

Pin Count

Operating Temperature (min)

-40C

Operating Temperature (max)

85C

Operating Temperature Classification

Industrial

Lead Free Status / RoHS Status

Not Compliant

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MC100LVEL90

−3.3V / −5V Triple ECL Input

to LVPECL Output Translator

Description

receives either −3.3 V or −5 V differential ECL signals, determined by the

output signals.

rails. The V

pins, as expected, are connected to the system ground plane. Both V

and V

the D input will be pulled to V

to a LOW, ensuring stability.

device only. For single-ended input conditions, the unused differential

input is connected to V

rebias AC coupled inputs. When used, decouple V

0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When

not used, V

Features

•

*For additional information on our Pb−Free strategy and soldering details, please

November, 2006 − Rev. 11

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

The MC100LVEL90 is a triple ECL to LVPECL translator. The device

To accomplish the level translation, the LVEL90 requires three power

Under open input conditions, the D input will be biased at V

The V

Pb Pkg

Pb−Free Pkg

For Additional Information, see Application Note AND8003/D

Oxygen Index: 28 to 34

500 ps Propagation Delays

ESD Protection: >2 kV HBM, >200 V MM

The 100 Series Contains Temperature Compensation

Operating Range: V

Internal Input Pulldown Resistors

Q Output will Default LOW with Inputs Open or at V

Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

Moisture Sensitivity;

Flammability Rating: UL 94 V−0 @ 0.125 in,

Transistor Count = 261 devices

Pb−Free Packages are Available*

supply level, and translates them to +3.3 V differential LVPECL

pin should be connected to the negative power supply. The GND

= −3.0 V to −5.5 V; GND = 0 V

should be bypassed to ground via 0.01 mF capacitors.

pin, an internally generated voltage supply, is available to this

should be left open.

supply should be connected to the positive supply, and the

Level 3

Level 1,

as a switching reference voltage. V

= 3.0 V to 3.8 V;

. This condition will force the Q output

and V

may also

/2 and

via a

*For additional marking information, refer to

See detailed ordering and shipping information in the package

dimensions section on page 5 of this data sheet.

Application Note AND8002/D.

ORDERING INFORMATION

MARKING DIAGRAM*

http://onsemi.com

AWLYYWWG

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

DW SUFFIX

CASE 751D

SO−20 WB

100LVEL90

Publication Order Number:

MC100LVEL90/D

Related parts for MC100LVEL90DWR2

MC100LVEL90DWR2 Summary of contents

Page 1

... Transistor Count = 261 devices • Pb−Free Packages are Available* *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2006 November, 2006 − Rev and ...

Page 2

GND LVPECL LVPECL ECL ECL All V pins are tied together on the die. CC Warning: All ...

Page 3

Table 3. NECL INPUT DC CHARACTERISTICS Symbol Characteristic I V Power Supply Current Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended) IL ECL V Output Voltage Reference BB V Input HIGH Voltage Common Mode IHCMR ...

Page 4

Table 5. AC CHARACTERISTICS V Symbol Characteristic fmax Maximum Toggle Frequency t Propagation Delay PLH PHL t Skew Output−to−Output (Note 5) SKEW Part−to−Part (Diff) (Note 5) Duty Cycle (Diff) (Note 6) tJITTER Random Clock Jitter V ...

Page 5

... ORDERING INFORMATION Device MC100LVEL90DW MC100LVEL90DWG MC100LVEL90DWR2 MC100LVEL90DWR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D AN1406/D AN1503/D AN1504/D AN1568/D AN1672/D AND8001/D − Odd Number Counters Design AND8002/D − ...

Page 6

... Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...

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