54ABT573J-QML National Semiconductor, 54ABT573J-QML Datasheet - Page 2
![no-image](/images/manufacturer_photos/0/4/469/national_semiconductor_sml.jpg)
54ABT573J-QML
Manufacturer Part Number
54ABT573J-QML
Description
Manufacturer
National Semiconductor
Type
D-Typer
Datasheet
1.54ABT573J-QML.pdf
(12 pages)
Specifications of 54ABT573J-QML
Logic Family
ABT
Number Of Bits
8
Number Of Elements
1
Latch Mode
Transparent
Polarity
Non-Inverting
Technology
BiCMOS
Package Type
CDIP
Propagation Delay Time
7.7ns
Operating Supply Voltage (typ)
5V
High Level Output Current
-24mA
Low Level Output Current
48mA
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temp Range
-55C to 125C
Operating Temperature Classification
Military
Mounting
Through Hole
Pin Count
20
Output Type
3-State
Lead Free Status / RoHS Status
Not Compliant
www.national.com
Functional Description
The ’ABT573 contains eight D-type latches with TRI-STATE
output buffers. When the Latch Enable (LE) input is HIGH,
data on the D
latches are transparent, i.e., a latch output will change state
each time its D input changes. When LE is LOW the latches
store the information that was present on the D inputs a
setup time preceding the HIGH-to-LOW transition of LE. The
TRI-STATE buffers are controlled by the Output Enable (OE)
input. When OE is LOW, the buffers are in the bi-state mode.
When OE is HIGH the buffers are in the high impedance
mode but this does not interfere with entering new data into
the latches.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
n
inputs enters the latches. In this condition the
2
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
O
0
= Value stored from previous clock cycle
OE
H
L
L
L
Inputs
LE
H
H
L
X
Function Table
D
H
L
X
X
Outputs
DS100219-3
O
O
H
L
Z
0