54F283FM National Semiconductor, 54F283FM Datasheet - Page 2

• Manufacturer Part Number: 54F283FM
• Manufacturer: National Semiconductor

Specifications of 54F283FM

• Logic Family: F
• Logical Function: Binary Full Adder
• Technology: Bipolar
• Number Of Elements: 1
• Number Of Bits: 4
• Propagation Delay Time: 17ns
• High Level Output Current: -1mA
• Low Level Output Current: 20mA
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: -55C to 125C
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Pin Count: 16
• Mounting: Surface Mount
• Operating Temperature Classification: Military
• Lead Free Status / RoHS Status: Not Compliant

Unit Loading Fan Out
Functional Description
The ’F283 adds two 4-bit binary words (A plus B) plus the
incoming Carry (C
(S
of the various inputs and outputs is indicated by the sub-
script numbers representing powers of two
Interchanging inputs of equal weight does not affect the op-
eration Thus C
5 6 and 7 for DIPS and 7 8 and 9 for chip carrier packages
Due to the symmetry of the binary add function the ’F283
can be used either with all inputs and outputs active HIGH
(positive logic) or with all inputs and outputs active LOW
(negative logic) See Figure 1 Note that if C
must be tied LOW for active HIGH logic or tied HIGH for
active LOW logic
Due to pin limitations the intermediate carries of the ’F283
are not brought out for use as inputs or outputs However
0
Pin Names
A
B
C
S
C
–S
0
0
0
0
4
–A
–B
–S
3
) and outgoing carry (C
3
3
3
Active HIGH 0
e
2
Logic Levels
Active HIGH
Active LOW
0
a
S
(A
0
0
2
0
2
a
A
0
a
) The binary sum appears on the Sum
(A
0
Where (
A Operand Inputs
B Operand Inputs
Carry Input
Sum Outputs
Carry Output
2S
B
2
B
a
Description
0
a
1
0
a
a
can be arbitrarily assigned to pins
10
B
2
C
4S
a
a
C
)
0
L
0
1
a
0
)
9
4
2
)
) outputs The binary weight
a
e
e
a
2
FIGURE 1 Active HIGH versus Active LOW Interpretation
3
3
2
plus
A
8S
1
(A
L
0
1
a
0
(A
3
3
16
1
a
a
a
A
H
1
0
B
16C
1
Active LOW 1
B
3
HIGH LOW
0
)
1
4
is not used it
50 33 3
50 33 3
)
1 0 2 0
1 0 2 0
1 0 1 0
A
U L
L
0
1
2
A
H
1
0
a
3
54F 74F
5
a
B
H
1
0
6
0
2
20 A
20 A
20 A
Output I
b
b
e
Input I
1 mA 20 mA
1 mA 20 mA
12
Figure 5 shows one method of implementing a 5-input ma-
other means can be used to effectively insert a carry into or
bring a carry out from an intermediate stage Figure 2
shows how to make a 3-bit adder Tying the operand inputs
of the fourth adder (A
on and equal to the carry from the third adder Using some-
what the same principle Figure 3 shows a way of dividing
the ’F283 into a 2-bit and a 1-bit adder The third stage
adder (A
carry (C
bringing out the carry from the second stage on S
that as long as A
LOW they do not influence S
are the same the carry into the third stage does not influ-
ence the carry out of the third stage Figure 4 shows a meth-
od of implementing a 5-input encoder where the inputs are
equally weighted The outputs S
ry number equal to the number of inputs I
jority gate When three or more of the inputs I
the output M
B
L
0
1
a
1
b
b
b
0
IH
OH
1 2 mA
1 2 mA
0 6 mA
B
L
0
1
I
10
2
IL
I
2
OL
) signal into the fourth stage (via A
B
2
5
B
H
1
0
is true
3
S
2
2
) is used merely as a means of getting a
S
and B
H
1
0
0
3
B
3
2
S
H
1
0
) LOW makes S
1
are the same whether HIGH or
2
0
S
L
0
1
Similarly when A
2
S
1
and S
S
L
0
1
3
1
3
2
–I
dependent only
present a bina-
C
5
H
1
0
2
1
4
that are true
and B
–I
5
2
are true
2
and B
2
) and
Note
2