CYIL2SM1300AA-GWCES Cypress Semiconductor Corp, CYIL2SM1300AA-GWCES Datasheet - Page 10

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CYIL2SM1300AA-GWCES

Manufacturer Part Number
CYIL2SM1300AA-GWCES
Description
Manufacturer
Cypress Semiconductor Corp
Type
CMOSr
Datasheet

Specifications of CYIL2SM1300AA-GWCES

Sensor Image Color Type
Monochrome
Sensor Image Size Range
>= 480,000Pixels
Sensor Image Size
1280x1024Pixels
Operating Supply Voltage (typ)
2.5V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Through Hole
Lead Free Status / RoHS Status
Not Compliant
Analog Front End
Programmable Gain Amplifiers
The PGAs amplify the signal before sending it to the ADCs.
The amplification inside the PGA is controlled by one SPI setting:
afemode [5:3].
Six gain steps can be selected by the afemode<5:3> register.
Table 7
PGA is done by the default afemode<5:3> setting.
Table 7. Gain Settings
Document Number: 001-24599 Rev. *E
afemode<5:3>
000
001
010
100
101
lists the six gain settings. The unity gain selection of the
011
Gain
2.25
1.5
1
2
3
4
Figure 7. Data Block
Analog to Digital Converter
The sensor has 24 10-bit pipelined ADCs on board. The ADCs
nominally operate at 31.5 Msamples/s.
Table 8. ADC Parameters
Data Block
The data block is positioned in between the analog front end
(output stage+ADCs) and the LVDS interface. It muxes the
outputs of two ADCs to one LVDS block and performs some
minor data handling:
It also contains a huge part of the functionality for black level
calibration and FPN correction.
A number of data blocks are placed in parallel to serve all data
output channels. One additional channel generates the synchro-
nization protocol. A high level overview is illustrated in the
following figure.
Data rate
Quantization
DNL
INL
CRC calculation and insertion
Training and test pattern generation
Parameter
31.5 Msamples/s
10 bit
Typ. < 1 DN
Typ. < 1 DN
Specification
CYIL2SM1300AA
Page 10 of 43
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