IP-POSPHY/L3 Altera, IP-POSPHY/L3 Datasheet - Page 31

• Manufacturer Part Number: IP-POSPHY/L3
• Manufacturer: Altera

Specifications of IP-POSPHY/L3

• Lead Free Status / RoHS Status: Not Compliant

Chapter 3: Functional Description
Example Implementations
Example Implementations
© November 2009 Altera Corporation
Figure 3–5
bit POS-PHY level 3 or 16-bit POS-PHY level 2.
Figure 3–5. Example Configuration 2—POS-PHY Bridging Functions
Figure 3–6 on page 3–3
an MPHY POS-PHY level 2 interface and one first-in first-out (FIFO) buffer per
supported address (MPHY).
Figure 3–6. Example Configuration 3—MPHY to MPHY Bridge
Figure 3–7
shows a bridging function with multiple lower-rate ports, which can be 8-
shows the FPGA interfacing to an OC-48 framer.
100 MHz
8 bit
100 MHz
32 bit
MegaCore Function 1
shows an MPHY to MPHY POS-PHY bridge, which includes
Interface
Level 3
PHY
MegaCore Function 1
Preliminary
Interface
Level 3
Link
FIFO
FIFO
FIFO
FIFO
FIFO
FIFO
Interfaces
Atlantic
MegaCore Function 2
Interface
Level 2
Link
POS-PHY Level 2 and 3 Compiler User Guide
Interface
Interface
Interface
Level 2
Level 2
Level 3
PHY
PHY
PHY
100 MHz
50 MHz
50 MHz
16 bit
16 bit
8 bit
50 MHz
16 bit
3–3