MC9328MX1DVH20 Freescale, MC9328MX1DVH20 Datasheet - Page 96

• Manufacturer Part Number: MC9328MX1DVH20
• Manufacturer: Freescale

Specifications of MC9328MX1DVH20

• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently
are not available from Freescale for import or sale in the United States prior to September 2010: i.MX1 Product Family
5
Table 44
Multiplexing Table 3 on page 11.
1
2
3
M
A
B
C
D
E
F
G
H
J
K
L
N
P
R
T
ASP signals are clamped by AVDD2 to prevent ESD (Electrostatic Discharge) damage. AVDD2 must be greater than QVDD to keep diodes reversed-biased.
This signal is not used and should be floated in an actual application.
burst clock
NVSS
NVSS
A24
A23
A22
A20
A18
A15
A13
A12
A10
EB2
A8
A5
A4
A3
1
1
Pin-Out and Package Information
illustrates the package pin assignments for the 256-pin MAPBGA package. For a complete listing of signals, see the Signal
SD_DAT3
SD_DAT1
D31
D30
A21
D27
A17
D22
A11
D16
D12
EB1
EB3
A7
D9
A2
2
2
SD_DAT0
SD_CMD
SD_CLK
D29
D28
D25
D24
A14
D18
D13
D11
D10
EB0
OE
A9
A1
3
3
SIM_SVEN
SIM_TX
SIM_PD
NVSS
CS3
CS4
CS5
D26
A19
D23
D20
D19
D17
D15
A6
D7
4
4
SD_DAT2
SUSPND
USBD_
USBD_
USBD_
USBD_
NVDD1
NVDD1
NVDD1
SDCLK
AFE
ROE
RCV
CS2
A16
D21
D14
A0
D6
D8
5
5
Table 44. i.MX1 256 MAPBGA Pin Assignments
USBD_VP
USBD_VM
SIM_RST
UART2_
SIM_RX
NVDD4
USBD_
NVDD1
NVDD1
NVDD1
NVSS
NVSS
CTS
VPO
ECB
CS1
D4
D5
6
6
SSI_RXCLK SSI_TXCLK
SIM_CLK
UART2_
UART2_
UART2_
USBD_
NVSS
NVSS
NVSS
NVSS
NVSS
PA17
VMO
RXD
RTS
TXD
LBA
CS0
RW
D2
7
7
SSI_RXDAT
SSI_TXDAT
SSI_TXFS
UART1_
UART1_
NVDD1
NVDD1
BCLK
QVSS
RXFS
MA10
MA11
SSI_
RTS
CTS
CAS
D1
D3
8
8
3
SPI_RDY
SPI1_SS
UART1_
UART1_
QVDD1
NVDD2
SPI1_
SPI1_
SPI1_
SPI1_
NVSS
DQM1
DQM3
DQM2
SCLK
MISO
MOSI
RXD
TXD
TCK
RAS
D0
9
9
RESET_SF
RESET_IN
BTRFGND
SDCKE1
NVDD3
NVDD2
SDWE
NVSS
DQM0
BT11
BT13
BT12
BT10
BT9
TIN
PS
10
10
2
SDCKE0
ENDIAN
RESET_
PWMO
BOOT3
CLKO
LD10
BIG_
OUT
BT5
BT7
BT8
BT6
BT4
BT2
CLS
LD0
LD6
11
11
CONTRAST
CSI_MCLK
BTRFVDD
CSI_D4
BOOT2
BOOT0
AVDD1
LD12
N.C.
N.C.
REV
POR
BT3
BT1
LD2
LD7
12
12
TRISTATE
ACD/OE
QVDD4
CSI_D0
HSYNC
PIXCLK
BOOT1
QVSS
TRST
LD13
N.C.
N.C.
N.C.
CSI_
CSI_
PY1
LD4
LD8
13
13
CSI_VSYNC
EXTAL16M
I2C_SCL
AVDD2
HSYNC
CSI_D1
CSI_D7
LD11
LD14
RVP
RVM
N.C.
TDO
PY2
PX1
LD5
LP/
14
14
1
TMR2OUT
XTAL16M
I2C_SDA
VSYNC
QVDD3
CSI_D2
CSI_D6
QVDD2
LSCLK
FLM/
VSS
R1A
TMS
UIP
UIN
PX2
LD9
15
15
EXTAL32K
SPL_SPR
XTAL32K
CSI_D3
CSI_D5
QVSS
QVSS
R2B
R2A
LD15
N.C.
N.C.
R1B
LD1
LD3
TDI
16
16
A
B
C
D
E
F
G
H
K
L
M
N
P
R
T
J