QG80333M500 S L8CC Intel, QG80333M500 S L8CC Datasheet - Page 31

• Manufacturer Part Number: QG80333M500 S L8CC
• Manufacturer: Intel

Specifications of QG80333M500 S L8CC

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Specification Changes
1.
Issue:
2.
Issue:
Specification Update
Recommended DLL register values
Using the default DLL values in combination with low duty cycle DIMMs may result in low hold
time margins on read transactions.
The default values for the DLL master and slave registers do not center the internal DQS with
respect to the eye of the incoming data. Using the default values may result in a reduced hold time
due to DQS being late in the data eye, which could lead to ECC errors. Errors have only been
observed when using DIMMs that have a low DQS duty cycle.
Note: All of the Intel validation up to this point has been with the default, worst case DLL values
and all DIMMs used in validation have passed.
Firmware should be updated and tested with these new DLL values, in order to add margin to the
hold timing during memory reads.
DDR-II 400 settings
SLVLMIX0 - Address FFFF_F554h; Recommended value - 3333_3333h
SLVLMIX1 - Address FFFF_F558h; Recommended value - 0000_0003h
SLVHMIX0 - Address FFFF_F55Ch; Recommended value - 3333_3333h
SLVHMIX1 - Address FFFF_F560h; Recommended value - 0000_0003h
SLVLEN - Address FFFF_F564h; Recommended value - 0000_0003h
MASTMIX - Address FFFF_F568h; Recommended value - 0000_000Ah
MASTLEN - Address FFFF_F56Ch; Recommended value - 0000_0002h
DDR-I 333 settings
SLVLMIX0 - Address FFFF_F554h; Recommended value - 6666_6666h
SLVLMIX1 - Address FFFF_F558h; Recommended value - 0000_0006h
SLVHMIX0 - Address FFFF_F55Ch; Recommended value - 6666_6666h
SLVHMIX1 - Address FFFF_F560h; Recommended value - 0000_0006h
SLVLEN - Address FFFF_F564h; Recommended value - 0000_0003h
MASTMIX - Address FFFF_F568h; Recommended value - 0000_0000h
MASTLEN - Address FFFF_F56Ch; Recommended value - 0000_0002h
DDR-II JEDEC initialization sequence includes writes to EMRS2 and EMRS3
The JEDEC DDR-II specification includes a write to EMRS2 and EMRS3 (Extended Mode
Register Set) during the initialization sequence. Step 5 is ‘Issue EMRS2 command’ and step 6 is
‘Issue EMRS3 command’. In order to be JEDEC compliant, these steps should be added to the
memory controller initialization sequence.
Note: Before implementing, check with your DIMM/memory manufacturer to determine if these
steps are necessary. Software should always follow the initialization sequence provided by the
DIMM/memory manufacturer guidelines.
The following pseudo code shows the EMRS initialization steps that are required to be compliant
with the JEDEC DDR-II initialization sequence.
// Step 5 and 6 - EMRS(2) and EMRS(3) programming
Intel® 80333 I/O Processor
Specification Changes
31