MCIMX31VKN5 Freescale, MCIMX31VKN5 Datasheet - Page 62
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MCIMX31VKN5
Manufacturer Part Number
MCIMX31VKN5
Description
Manufacturer
Freescale
Datasheet
1.MCIMX31VKN5.pdf
(122 pages)
Specifications of MCIMX31VKN5
Operating Temperature (min)
0C
Operating Temperature (max)
70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Part Number:
MCIMX31VKN5
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Freescale Semiconductor
Quantity:
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Part Number:
MCIMX31VKN5B
Manufacturer:
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Company:
Part Number:
MCIMX31VKN5BR2
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Quantity:
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Company:
Part Number:
MCIMX31VKN5C
Manufacturer:
FREESCA
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18
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Freescale Semiconductor
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FREESCALE
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Part Number:
MCIMX31VKN5CR2
Manufacturer:
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Quantity:
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Electrical Characteristics
Table 47
1
Display interface clock period average value.
62
Display interface clock period immediate value.
DISPB_D3_HSYNC
DISPB_D3_VSYNC
DISPB_D3_DRDY
IP10
IP11
IP12
IP13
IP14
IP15
IP5
IP6
IP7
IP8
IP9
ID
Tdicp
shows timing parameters of signals presented in
=
Display interface clock period
Display pixel clock period
Screen width
HSYNC width
Horizontal blank interval 1
Horizontal blank interval 2
HSYNC delay
Screen height
VSYNC width
Vertical blank interval 1
Vertical blank interval 2
⎧
⎪
⎪
⎨
⎪
⎪
⎩
IP11
T HSP_CLK
Table 47. Synchronous Display Interface Timing Parameters—Pixel Level
T HSP_CLK
Figure 48. TFT Panels Timing Diagram—Vertical Sync Pulse
Parameter
⋅
⎛
⎝
floor
⋅
DISP3_IF_CLK_PER_WR
----------------------------------------------------------------- -
IP13
HSP_CLK_PERIOD
Tdicp
DISP3_IF_CLK_PER_WR
----------------------------------------------------------------- -
MCIMX31/MCIMX31L Technical Data, Rev. 4.1
HSP_CLK_PERIOD
=
T HSP_CLK
IP14
Symbol
Tdpcp
Thbi1
Thbi2
Tdicp
Thsw
Tvbi1
Tvbi2
Thsd
Tvsw
Tsw
⋅
Tsh
,
DISP3_IF_CLK_PER_WR
----------------------------------------------------------------- -
HSP_CLK_PERIOD
+
0.5 0.5
Figure 47
±
Tdicp
(DISP3_IF_CLK_CNT_D+1) * Tdicp
(SCREEN_WIDTH+1) * Tdpcp
(H_SYNC_WIDTH+1) * Tdpcp
BGXP * Tdpcp
(SCREEN_WIDTH – BGXP – FW) * Tdpcp
H_SYNC_DELAY * Tdpcp
(SCREEN_HEIGHT+1) * Tsw
if V_SYNC_WIDTH_L = 0 than
(V_SYNC_WIDTH+1) * Tdpcp
else
(V_SYNC_WIDTH+1) * Tsw
BGYP * Tsw
(SCREEN_HEIGHT – BGYP – FH) * Tsw
⎞
⎠
Start of frame
1
,
IP12
for integer
for fractional
and
Figure
Value
DISP3_IF_CLK_PER_WR
----------------------------------------------------------------- -
HSP_CLK_PERIOD
DISP3_IF_CLK_PER_WR
----------------------------------------------------------------- -
48.
HSP_CLK_PERIOD
End of frame
Freescale Semiconductor
IP15
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns