MCIMX356AJM5B Freescale, MCIMX356AJM5B Datasheet - Page 50

• Manufacturer Part Number: MCIMX356AJM5B
• Manufacturer: Freescale

Specifications of MCIMX356AJM5B

• Lead Free Status / RoHS Status: Compliant

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SD10 and SD11 are determined by SDRAM controller register settings.
SD10
SD11
SD7
ID
SDCLK
CAS
CKE
ADDR
RAS
WE
CS
Address hold time
Precharge cycle period
Auto precharge command period
SDR SDRAM CLK parameters are measured from the 50% point—that is,
“high” is defined as 50% of signal value and “low” is defined as 50% of
signal value.
The timing parameters are similar to the ones used in SDRAM data sheets.
Table 35
the ESDCTL at the negative edge of SDCLK, and the parameters are
measured at maximum memory frequency.
Don’t care
BA
i.MX35 Applications Processors for Automotive Products, Rev. 9
Table 35. SDRAM Refresh Timing Parameters (continued)
indicates SDRAM requirements. All output signals are driven by
Figure 30. SDRAM Self-Refresh Cycle Timing Diagram
1
Parameter
SD16
1
NOTE
Symbol
tAH
tRP
tRC
SD16
Min.
1.8
1
2
Freescale Semiconductor
Max.
20
—
4
clock
clock
Unit
ns