MC68882RC25A Freescale, MC68882RC25A Datasheet - Page 12

• Manufacturer Part Number: MC68882RC25A
• Manufacturer: Freescale

Specifications of MC68882RC25A

• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

....-
:$Q~*ESS
‘&#rdetails).
the MC68882
strapped
formation,
quests for $~~J~@’&ccur as standard
syste~%at%~,bbs.
conJ~@~~{a@n, both the AO and SIZE pins are configured
SIZE (SIZE)
the AO pin to configure
bit data bus, the AO pin is used as an address signal for
byte accesses of the coprocessor
bit system
DATA BUS (DO through
general
MC68030
MC68882
processor,
s~:~?t~a”lly for the applicable
an 8-, 16-, or 32-bit system data bus. When the MC68882
is configured
bus, both the SIZE and AO pins are strapped
low as listed in Table 4.
$$j
A4-AO
When the MC68882 is configured
This 32-bit, bidirectional,
The MQ@,*~will
This active-low
Oooox
Ooolx
Oolox
Oollx
Oloox
Ololx
Ollox
Olllx
1Ooxx
101OX
Iollx
11Oxx
Illxx
Table 4. System Data Bus Size Configuration
purpose
high and/or
and the MC~~&~.’’’Regardless
is operat~d
Offset
BUS (AO through A4) and SIZE (SIZE) for fur-
all in~,@$@o,gessor transfers
data bus, both the AO and the SIZE pins are
$OA
$Oc
$OE
$lC
$00
$02
$04
$06
$08
$10
$14
$16
$18
op~r,~~d$$~ata,
High
Low
Table 3. Coprocessor
AO
—
t~erate
is configured
input signal is used in conjunction
Depending
Register
Mdth
data,~~~h,~etween
32
32
32
16
16
16
16
16
16
16
16
16
16
operate
low as listed in Table 4.
a~$~’coprocessor
the MC68882 for operation
D31 ) ~~” ‘“~~
SIZE
High
High
over a 16- or 32-bit system data
Low
+~k~%%~bte bus serves as the
status
Write
Write
Write
Selection
to operate
Type
Read
Read
Read
Read
R~
Rfi
RR
–
–
–
bus configuration.
upon the system data bus
Freescale Semiconductor, Inc.
over an 8-, 16-, or 32-bit
interface registers. When
For More Information On This Product,
,, , 4). > ‘ ‘%;V, $~$
Intetiace
Command
Condition
information,
Response
Control
Save
Restore
(Reserved)
(Reserved)
Operand
Register Select
(Reserved)
Instruction Address
Operand Address
to operate over an 8-
,,..:..
,. ‘\\.~J~.\
Data Bus
M68000 bus cycles.
.~~,;~y$.
16-Bi~$$’Q$y‘?’
3~*qk$;,.~’
over a f16- or 32-
8-Bit
of instruction
.’~:i,>
the
or a peripheral
.,?, .. .
of whether
Register
Go to: www.freescale.com
..*.,,, ,,.,,,
high and/or
MC68020/
.tt,.
:.
*
(Refer to
.; ‘>:,},
and
,$~$’
~
*>:.,.
with
over
the
in-
re-
~i$t
,:’
*$rS$$upon
i$$it,~@8882
‘-l?+
..?~,,c&hpletion
the MC68882, DSACKO and DSACKI are used to acknowl-
ADDRESS STROBE (AS)
valid address on the address bus, and both the chip select
(CS) and read/write
CHIP SELECT (CS)
access to the MC68882 coprocessor
When operating
the chip select decode is system dependent
chip select on any peripheral).
READ/WRITE (R/~)
action
(1) indicates
(0) indicates
be valid when AS is ass@Xl@+~j:
DATA STROBE (DS)’:Xj~,~,t.$~
data on the
asserts DSACKO and DSACKI
information on the data bus is valid. (Both DSACK signals
may be asserted in advance of the valid data being placed
on the bus. ) If the bus cycle is a main processor
edge acceptance
to dynamically
“port”
basis, Depending
asserted in a given bus cycle, the MC68020/MC68030
sumes data has been transferred
32-bit wide data port. Table 5 lists the DSACK assertions
that are used by the MC68882 for the various
over the various
where A4 equals zero are to 16-bit registers, The MC68882
data lines
word addresses
for 32-bit bus operation,
signals
order to reduce the signal
implements
multi plexers);
16-bit registers
DO-DI 5. For accesses to these registers when configured
MC68030 of valid data on D16-D31 instead of DO-D15.
both DSACKO and DSACKI
DSACKI
~Kese
This active-low
This input signal indicates
This active-lowin:~~~ignal
The MC68882 also uses DSACKO and DSACKI signals
This active-low
If the bus cycle is a main processor
Table 5 indicates
An external
assertion
(read/write)
size (system data bus width)
‘?,
as listed
active-low,
lines are actively
asserts b~h the DSACKO and DSACKI signals
D16-D31
d~~~:~ys
a w~te to the ~~~8&The
all 16-bit coprocessor
a read from the @8,@~,
however,
holding
of a bus cycle to the main processor. The
of CS.
that are located
indicate
(Al = 1) to be implemented
the MC68882 as a peripheral
system data bus configurations.
input signal enables the main processor
of the data by the MC68882.
,;~.>t,, . ,>+f,
upon which of the two DSACK pins are
input
in Table
by the main~f~~~sbr.
(R~)
that all accesses over a 32-bit
(to eliminate
three-state
~:<:~,..
during
.‘X., ,,\ -$:
~..+ “ .**,?,)$.!+
..,/ ,
resistor
signal
the MC68020/MC68030
the MC68882 generates
to the MC68020/MC68030
signal lines are valid.
high between
pulled
5 to inform
rise time,
the di~~8]o~#@Y a bus trans-
a
indicates that there is valid
signals to indicate that the
write bus cycle.
indicates
is required
output
in a 32-bit
to/from
the need for on-chip
interface
up (negated)
!,.’.t..i~..,!
on a cycle-by-cycle
interface
read, the MC68882
*;>K:,, ‘:3,. “~ ~
the DSACKO and
RN signal must
signals
,h+.t.::~,
an~ a logic low
that there is a
.?;.l\ .,,.\$, ~\...:~
the MC68020/
bus cycles. In
an 8-, 16-, or
‘%$,,
on data lines
~;,
A logic high
.\\!.+’*: >},i,~ ??
(i.~~~j~$the
registers
to maintain
.
port at odd
pro$essor,
bus cycles
..$’s,*k.
registers.
“...,
indicate
write to
expects
DSACK
by the
bus
the
as-
on
r
~:-
.::. :Y
...