MC9328MX21SVM Freescale, MC9328MX21SVM Datasheet

Page 1

... For cost sensitive applications, the NAND Flash controller allows the use of low-cost NAND Flash This document contains information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2005–2008. All rights reserved. Document Number: MC9328MX21S MC9328MX21S Package Information (MAPBGA– ...

Page 2

... Bus Control Internal Control Memory Control Memory Interface SDRAMC LCD Controller WEIM SLCD Controller NFC Keypad MC9328MX21S Technical Data, Rev. 1.3 Connectivity CSPI x 2 SSI Audio Mux UART 1, 3, & 4 1-Wire FIRI USB OTG/ 1 Host Memory Expansion MMC/ PCMCIA/CF Freescale Semiconductor ...

Page 3

... Part Order Number MC9328MX21SVK 289-lead MAPBGA 0.65mm, 14mm x 14mm MC9328MX21SCVK 289-lead MAPBGA 0.65mm, 14mm x 14mm MC9328MX21SVM 289-lead MAPBGA 0.8mm, 17mm x 17mm MC9328MX21SCVM 289-lead MAPBGA 0.8mm, 17mm x 17mm 1.4 Features The i.MX21S boasts a robust array of features that can support a wide variety of applications. Below is a brief description of i.MX21S features. • ...

Page 4

... If not utilizing these signals for GPIO functionality or for their other multiplexed function, then configure as GPIO input with pull up enabled, and leave connect. • TEST_WB[4:3]: To ensure proper operation, leave these signals as no connects. 4 depends solely upon the user application, however there are a few MC9328MX21S Technical Data, Rev. 1 Section 4, “Pin Freescale Semiconductor ...

Page 5

... SDRAM Chip Select signal. This signal is multiplexed with the CS3 signal. This signal is selectable by programming the Function Multiplexing Control Register in the System Control chapter. RAS SDRAM Row Address Select signal. Freescale Semiconductor Table 2. i.MX21S Signal Descriptions Function/Notes External Bus/Chip Select (EIM) ...

Page 6

... JTAG Controller select signal—JTAG_CTRL is sampled during the rising edge of TRST. Must be pulled to logic high for proper JTAG interface to debugger. Pulling JTAG_CRTL low is for internal test purposes only. 6 Function/Notes Clocks and Resets JTAG MC9328MX21S Technical Data, Rev. 1.3 ® ® User Guide from ARM Limited. Freescale Semiconductor ...

Page 7

... SLCDC Register Select input signal for pass through to SLCD device. This signal is multiplexed with SSI3_RXD signal from SSI3. SLCDC2_D0 SLCD Data input signal for pass through to SLCD device. This signal is multiplexed with SSI3_FS signal from SSI3. Freescale Semiconductor Function/Notes LCD Controller Smart LCD Controller MC9328MX21S Technical Data, Rev. 1.3 ...

Page 8

... PCMCIA IO Read output signal. This signal is shared with EB3 of EIM. PC_IOWR PCMCIA IO Write output signal. This signal is shared with OE signal of EIM. PC_WP PCMCIA Write Protect input signal. This signal is multiplexed with NFIO[3] signal of NF. 8 Function/Notes External DMA NAND Flash Controller PCMCIA Controller MC9328MX21S Technical Data, Rev. 1.3 Freescale Semiconductor ...

Page 9

... USB OTG Transceiver ON output signal. This signal is muxed with SLCDC1_DAT9. USBG_FS USB OTG Full Speed output signal. This signal is multiplexed with external transceiver USBG_TXR_INT signal of USB OTG. This signal is muxed with SLCDC1_DAT10. Freescale Semiconductor Function/Notes CSPI General Purpose Timers USB On-The-Go MC9328MX21S Technical Data, Rev ...

Page 10

... Receive Data input signal which is multiplexed with USBH1_RXDP and USBH1_TXDP. UART4_TXD Transmit Data output signal which is multiplexed with USBH1_TXDM. UART4_RTS Request to Send input signal which is multiplexed with USBH1_FS and USBH1_RXDP. 10 Function/Notes Secure Digital Interface UARTs – IrDA/Auto-Bauding MC9328MX21S Technical Data, Rev. 1.3 Freescale Semiconductor ...

Page 11

... Alternatively, KP_COL6 is also available on the internal factory test signal TEST_WB2. The Function Multiplexing Control Register in the System Control chapter must be used in conjunction with programming the GPIO multiplexing (to select the alternate signal multiplexing) to choose which signal KP_COL6 is available. Freescale Semiconductor Function/Notes 2 S protocol and AC97) ...

Page 12

... Ratings,” (Table Range” (Table 4) is not implied. Exposure to Table 3. Maximum Ratings Symbol QVDD QVDDX max, max NVDD VDDA max, max V Imax T storage MC9328MX21S Technical Data, Rev. 1.3 3) may cause Min Max Units -0.3 2.1 V -0.3 3 -0.3 VDD + 0 -55 150 C Freescale Semiconductor ...

Page 13

... Table 5 contains the DC characteristics of the i.MX21S. Parameter High-level input voltage Low-level Input voltage High-level output voltage Low-level output voltage High-level output current, slow I/O High-level output current, fast I/O Low-level output current, slow I/O Freescale Semiconductor Symbol Minimum NVDD x QVDD, QVDDx VDDA Table 5 ...

Page 14

... Max Units 5 pF – – Symbol Typ Max Units 120 – mA QVDD QVDDX I 8 – mA NVDD1 through 6.6 – mA NVDD6 VDDA I STBY 1 – 3.0 mA ° μA – 700 ° μA 320 – Freescale Semiconductor ...

Page 15

... EXTAL32k input jitter (peak to peak) for both System PLL and MCUPLL EXTAL32k input jitter (peak to peak) for MCUPLL only EXTAL32k startup time Table 10. CLKO Rise/Fall Time (at 30pF Loaded) Rise Time Fall Time Freescale Semiconductor to V under an operating temperature from T DD min DD max Maximum I/O Loading at 1.8 V ...

Page 16

... T ref 220 280 330 T ref 480 530 580 T ref 360 410 460 T ref – 0.02 0.03 2•T – 1.0 1.5 ns – 1.5 – mW (Avg) Freescale Semiconductor dck ...

Page 17

... RESET_DRAM HRESET RESET_OUT CLK32 HCLK Figure 2. Timing Relationship with POR RESET_IN HRESET RESET_OUT 6 CLK32 HCLK Figure 3. Timing Relationship with RESET_IN Freescale Semiconductor 1 2 Exact 300ms 5 MC9328MX21S Technical Data, Rev. 1.3 Specifications Figure 2 and 3 7 cycles @ CLK32 4 14 cycles @ CLK32 14 cycles @ CLK32 ...

Page 18

... DMA request is de-asserted immediately after sensing grant signal active. 18 1.8 V ± 0.10 V 3.0 V ± 0.30 V Min 800 300 MC9328MX21S Technical Data, Rev. 1.3 Unit Max Min Max – 800 – ms 300 300 300 Cycles of CLK32 Cycles of CLK32 – 4 – Cycles of CLK32 Cycles of CLK32 Figure 4 and Freescale Semiconductor ...

Page 19

... Control Register (PERIODREG2) can also be programmed to a fixed data transfer rate for either CSPI1 or CSPI2. When the CSPI1 module is configured as a slave, the user can configure the SPI 1 Control Register (CONTROLREG1) to match the external CSPI master’s timing. In this configuration, SS Freescale Semiconductor t min_assert ...

Page 20

... Figure 8. Master CSPI Timing Diagram Ignore SPI_RDY Level Trigger SS (input) SCLK, MOSI, MISO Figure 9. Slave CSPI Timing Diagram FIFO Advanced by BIT COUNT SS (input) 6 SCLK, MOSI, MISO Figure 10. Slave CSPI Timing Diagram FIFO Advanced by SS Rising Edge MC9328MX21S Technical Data, Rev. 1.3 Freescale Semiconductor ...

Page 21

... When CSTN, TFT or monochrome mode with bus width = 1, SCLK is equal to the pixel clock. When monochrome with other bus width settings, SCLK is equal to the pixel clock divided by bus width. The polarity of SCLK and LD can also be programmed. Maximum frequency of SCLK is HCLK / 3 for TFT and CSTN, otherwise LD output will be incorrect. Freescale Semiconductor Figure 6 through Parameter ...

Page 22

... XMAX (0,1) (0,2) (0,X-1) Minimum T5+T6+T7-1 – Figure MC9328MX21S Technical Data, Rev. 1.3 Display region Line Y T7 Value Unit (VWAIT1·T2)+T5+T6+T7-1 Ts XMAX+T5+T6+T7 Ts VWIDTH·T2 Ts (VWAIT2·T2)+1 Ts HWIDTH+1 Ts HWAIT2+3 Ts HWAIT1+1 Ts 12, all 3 signals are active low. Figure 12, SCLK is Freescale Semiconductor ...

Page 23

... REV toggle delay from last LD of line Note: • Falling of SPL/SPR aligns with first LD of line. • Falling of PS aligns with rising edge of CLS. • REV toggles in every HSYN period. Freescale Semiconductor XMAX Figure 13. Sharp TFT Panel Timing Table 17. Sharp TFT Panel Timing Minimum – ...

Page 24

... When monochrome mode with bus width = 2, 4, and and 4 Tpix respectively XMAX Ts Table 18. Non-TFT Mode Panel Timing Minimum 2 1 – 1 MC9328MX21S Technical Data, Rev. 1 Value Unit HWAIT2+2 Tpix HWIDTH+1 Tpix ≤ ≤ – HWAIT1+1 Tpix Figure 59, all these 3 signals are Freescale Semiconductor ...

Page 25

... RS T2 LCD_CS LCD_CLK (LCD_DATA[6]) SDATA (LCD_DATA[7 LCD_CS LCD_CLK (LCD_DATA[6]) SDATA (LCD_DATA[7]) RS Figure 15. SLCDC Serial Transfer Timing Freescale Semiconductor T1 T4 MSB T6 RS=0 ≥ command data, RS=1≥ display data SCKPOL = 1, CSPOL = MSB T6 RS=0 ≥ command data, RS=1≥ display data SCKPOL = 0, CSPOL = 0 ...

Page 26

... Register select setup time T5 Register select hold time 26 Minimum command data display data CSPOL = command data display data CSPOL = 1 Minimum MC9328MX21S Technical Data, Rev. 1.3 Maximum Unit 962 ns – ns – ns – ns – ns – ns – ns Maximum Unit 962 ns – ns – ns – ns – ns Freescale Semiconductor ...

Page 27

... Output hold time —10/30 cards 3 6b Output setup time —10/30 cards 3 7 Output delay time ≤ 100 pF / 250 pF (10/30 cards) L ≤ 250 pF (21 cards) L ≤ card) L Freescale Semiconductor Valid Data 7 Valid Data 6a 1.8 V ± 0.1 V Min 1 —10/30 cards 6/33 15/75 – 10/50 (5.00) – ...

Page 28

... Figure 18 Symbol S Data bits cycles ID CRC ****** Identification Timing N cycles CR CRC ****** MC9328MX21S Technical Data, Rev. 1.3 Figure 18 through through Figure 22 Host Active Definition Start bit (0) Transmitter bit (Host = 1, Card = 0) One-cycle pull-up (1) End bit (1) CID/OCR Content CID/OCR Content SET_RCA Timing and Freescale Semiconductor ...

Page 29

... SD_CMD lines as usual. Data transmission from the card starts after the access time delay N from the last bit of the read command. If the system is in multiple block read mode, the card sends a continuous flow of data blocks with distance N data stops two clock cycles after the end bit of the stop command. Freescale Semiconductor N cycles CR ...

Page 30

... Timing of single block read N cycles CR Response ****** Content CRC E Z ****** ***** P Read Data N cycles AC N cycles CR Response Content CRC ****** Content ***** Timing of stop command (CMD12, data transfer mode) MC9328MX21S Technical Data, Rev. 1.3 CRC E Z ***** ***** ***** Read Data N cycles AC Timing of multiple block read CRC E Z ***** Freescale Semiconductor ...

Page 31

... Figure 21. Timing Diagrams at Data Write The stop transmission command may occur when the card is in different states. different scenarios on the bus. Freescale Semiconductor MC9328MX21S Technical Data, Rev. 1.3 Specifications Figure 22 shows the 31 ...

Page 32

... MMC/SD bus clock, CLK (All values are referred to minimum (VIH) and maximum (VIL) Command response cycle Identification response cycle Access time delay cycle 32 Figure 18 through Symbol Minimum NCR 2 NID 5 NAC 2 MC9328MX21S Technical Data, Rev. 1.3 Figure 22 Maximum Unit 64 Clock cycles 5 Clock cycles TAAC + NSAC Clock cycles Freescale Semiconductor ...

Page 33

... CMD ****** DAT[1] Block Data For 4-bit DAT[2] Block Data For 4-bit Figure 24. SDIO ReadWait Timing Diagram Freescale Semiconductor Figure 18 through Figure 22 Symbol Minimum NRC 8 NCC 8 NWR 2 NST 2 S Response ...

Page 34

... NFIO[7:0] Figure 25. Command Latch Cycle Timing DIagram 34 Figure 28 depict the relative timing requirements among different Table 24 lists the timing parameters. The NAND Flash Controller NF1 NF2 NF3 NF4 NF5 NF6 NF7 NF9 NF8 command MC9328MX21S Technical Data, Rev. 1.3 Freescale Semiconductor ...

Page 35

... NFWE NF6 NFALE NFIO[15:0] Figure 27. Write Data Latch Timing DIagram NFCLE NFCE NFRE NFRB NFIO[15:0] Figure 28. Read Data Latch Timing Diagram Freescale Semiconductor NF4 NF5 NF7 NF8 NF9 Address Time it takes for SW to issue the next address command NF10 NF11 NF5 ...

Page 36

... Unit Max Min Max – 30 – ns – 30 – ns – 30 – ns – 30 – ns – 30 – ns – 30 – ns – 30 – ns – 30 – ns – 30 – ns – 60 – ns – 30 – ns – 120 – ns – 45 – ns – 60 – ns – 15 – ns – 15 – ns – 0 – ns Freescale Semiconductor ...

Page 37

... Clock high time 1 2b Clock low time 1 3a Clock fall time 1 3b Clock rise time 1 4a Output delay time 1 4b Output setup time PWMO = TBD L Freescale Semiconductor 1.8 V ± 0.1 V Minimum Maximum 0 45 12.29 – 9.91 – – 0.5 – 0.5 9.37 – ...

Page 38

... Note: CKE is high during the read/write cycle. 1.8 V ± 0.1 V Minimum Maximum 3.00 3.00 7.5 4.78 3.03 MC9328MX21S Technical Data, Rev. 1.3 2 3.0 V ± 0.3 V Unit Minimum Maximum – 3 – ns – 3 – ns – 7.5 – ns – 3 – ns – 2 – ns Freescale Semiconductor ...

Page 39

... SDRAM clock cycle time. The t RCD SDCLK RAS CAS ADDR / BA DQ DQM Figure 31. SDRAM Write Cycle Timing Diagram Freescale Semiconductor 1.8 V ± 0.1 V Minimum Maximum 3.67 2.95 – – – 2 – – – RCD setting can be found in the i.MX21S reference manual. ...

Page 40

... – RCD 3.41 – 2.45 – MC9328MX21S Technical Data, Rev. 1.3 3.0 V ± 0.3 V Unit Minimum Maximum 3 – – ns 7.5 – – – – – ns RCD 2 – – ROW/BA Freescale Semiconductor ...

Page 41

... SDRAM clock cycle time. These settings can be found in the i.MX21 reference manual SDCLK CS RAS CAS WE ADDR BA DQ DQM CKE Figure 33. SDRAM Self-Refresh Cycle Timing Diagram Freescale Semiconductor 1.8 V ± 0.1 V Minimum Maximum 3.00 – 3.00 – 7.5 – 3.67 – 2.95 – ...

Page 42

... The SSI can be connected to 4 set of ports, SAP, SSI1, SSI2 and SSI3. CK Output FS (bl) Output FS (wl) Output STXD Output SRXD Input Note: SRXD input in synchronous mode only. Figure 34. SSI Transmitter Internal Clock Timing Diagram 42 37 MC9328MX21S Technical Data, Rev. 1 Freescale Semiconductor ...

Page 43

... Figure 35. SSI Receiver Internal Clock Timing Diagram CK Input FS (bl) Input FS (wl) Input STXD Output SRXD Input Note: SRXD Input in Synchronous mode only Figure 36. SSI Transmitter External Clock Timing Diagram CK Input FS (bl) Input FS (wl) Input SRXD Input Figure 37. SSI Receiver External Clock Timing Diagram Freescale Semiconductor ...

Page 44

... Freescale Semiconductor ...

Page 45

... SRXD hold time after (Rx) CK low 1 15 (Tx/Rx) CK clock period 16 (Tx/Rx) CK clock high period 17 (Tx/Rx) CK clock low period 18 (Tx) CK high to FS (bl) high 19 (Rx) CK high to FS (bl) high Freescale Semiconductor 1.8 V ± 0.1 V Minimum Maximum 23.00 0 1.20 0 1.8 V ± 0.1 V Minimum Maximum 1 Internal Clock Operation (SSI1 Ports) 90 ...

Page 46

... V ± 0.3 V Unit Minimum Maximum – 90.91 – ns 0.01 0.15 ns -0.21 0.05 ns 0.01 0.15 ns -0.21 0.05 ns 0.01 0.15 ns -0.21 0.05 ns 0.01 0.15 ns -0.21 0.05 ns 0.34 0.72 ns Freescale Semiconductor ...

Page 47

... All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures. Freescale Semiconductor 1.8 V ± 0.1 V Minimum Maximum 0 ...

Page 48

... Freescale Semiconductor ...

Page 49

... When the presence pulse is detected, this bit will be cleared. The presence pulse is used by the bus master to determine if at least one DS2502 is connected. Software will determine if more than one DS2502 exists. The one-wire will sample for the DS2502 presence pulse. The presence pulse is latched in the one-wire Freescale Semiconductor 1.8 V ± 0.1 V Minimum Maximum 9 ...

Page 50

... After a Read, the control register RDST bit is set to the value of the read. 50 AutoClear WR0 Set WR0 Write 0 Slot 128us 17us 100us Figure 39. Write 0 Timing Auto Clear WR1/R Set WR1/RD Write “1” Slot 117us 5us Figure 40. Write 1 Timing MC9328MX21S Technical Data, Rev. 1.3 Freescale Semiconductor ...

Page 51

... This shows that the user should take care of the main clock frequency when using the one-wire module. If the main clock is an exact integer multiple of 1 MHz, then the generated frequency will be exactly 1 MHz. A main clock frequency below 10 MHz might cause a misbehavior of the module. Freescale Semiconductor Auto Clear WR1/RD Set WR1/RD Read “0” Slot 117us ...

Page 52

... TXDM_ OEB SE0 interval of EOP FEOPT Data transfer rate PERIOD PERIOD 2 Parameter MC9328MX21S Technical Data, Rev. 1 TXDM_OEB 3 t TXDP_OEB t FEOPT 5 3.0 V ± 0.3 V Unit Minimum Maximum 83.14 83.47 ns 81.55 81.98 ns 83.54 83.8 ns 248.9 249.13 ns 160 175 ns 11.97 12.03 Mb/s Freescale Semiconductor ...

Page 53

... Parameter 1 Hold time (repeated) START condition 2 Data hold time 3 Data setup time 4 HIGH period of the SCL clock 5 LOW period of the SCL clock 6 Setup time for STOP condition Freescale Semiconductor Minimum MC9328MX21S Technical Data, Rev. 1.3 Specifications 1 t FEOPR 3.0 V ± 0.3 V ...

Page 54

... EB (falling edge) LBA (negated falling edge) LBA (negated rising edge) Burst Clock (rising edge) Burst Clock (falling edge) Read Data Write Data (negated falling) Write Data (negated rising) DTACK 10a Figure 45. EIM Bus Timing Diagram MC9328MX21S Technical Data, Rev. 1 10a Freescale Semiconductor ...

Page 55

... Clock rise to Write Data Invalid 10a DTACK setup time 11 Burst Clock (BCLK) cycle time 1. Clock refers to the system clock signal, HCLK, generated from the System DPLL Freescale Semiconductor Table 38. EIM Bus Timing Parameters 1.8 V ± 0.1 V Min Typical 3.97 6.02 3.93 6 ...

Page 56

... Note: Signals listed with lower case letters are internal to the device. hclk hselm_weim_cs[0] htrans Seq/Nonseq hwrite haddr hready weim_hrdata weim_hready BCLK A[24:0] Last Valid Address CS[0] R/W LBA OE EB (EBC=0) EB (EBC=1) DATA_IN 56 Read V1 Last Valid Data Read Figure 46. WSC = 1, A.HALF/E.HALF MC9328MX21S Technical Data, Rev. 1 Freescale Semiconductor ...

Page 57

... Last Valid Data weim_hrdata weim_hready BCLK A[24:0] Last Valid Address CS[0] R/W LBA OE EB D[31:0] Last Valid Data Figure 47. WSC = 1, WEA = 1, WEN = 1, A.HALF/E.HALF Freescale Semiconductor Write Data (V1) Last Valid Data Write MC9328MX21S Technical Data, Rev. 1.3 Specifications Unknown V1 Write Data (V1) 57 ...

Page 58

... Read haddr V1 hready weim_hrdata Last Valid Data weim_hready BCLK A[24:0] Last Valid Addr CS[0] R/W LBA OE EB (EBC=0) EB (EBC=1) DATA_IN Figure 48. WSC = 1, OEA = 1, A.WORD/E.HALF 58 Address V1 Read 1/2 Half Word MC9328MX21S Technical Data, Rev. 1.3 V1 Word Address 2/2 Half Word Freescale Semiconductor ...

Page 59

... Last Valid Data weim_hrdata weim_hready BCLK A[24:0] Last Valid Addr CS[0] R/W LBA OE EB D[31:0] Figure 49. WSC = 1, WEA = 1, WEN = 1, A.WORD/E.HALF Freescale Semiconductor Write Data (V1 Word) Last Valid Data Address V1 1/2 Half Word MC9328MX21S Technical Data, Rev. 1.3 Specifications Address Write 2/2 Half Word 59 ...

Page 60

... Read haddr V1 hready weim_hrdata weim_hready BCLK A[24:0] Last Valid Addr CS[3] R/W LBA OE EB (EBC=0) EB (EBC=1) DATA_IN Figure 50. WSC = 3, OEA = 2, A.WORD/E.HALF 60 Last Valid Data Address V1 Read 1/2 Half Word MC9328MX21S Technical Data, Rev. 1.3 V1 Word Address 2/2 Half Word Freescale Semiconductor ...

Page 61

... BCLK A[24:0] Last Valid Addr CS[3] R/W LBA OE EB D[31:0] Last Valid Data Figure 51. WSC = 3, WEA = 1, WEN = 3, A.WORD/E.HALF Freescale Semiconductor Write Data (V1 Word) Last Valid Data Address V1 Write 1/2 Half Word MC9328MX21S Technical Data, Rev. 1.3 Specifications Address 2/2 Half Word 61 ...

Page 62

... Read haddr V1 hready weim_hrdata weim_hready BCLK A[24:0] Last Valid Addr CS[2] R/W LBA OE EB (EBC=0) EB (EBC=1) DATA_IN Figure 52. WSC = 3, OEA = 4, A.WORD/E.HALF 62 Last Valid Data Address V1 Read 1/2 Half Word MC9328MX21S Technical Data, Rev. 1.3 V1 Word Address 2/2 Half Word Freescale Semiconductor ...

Page 63

... BCLK A[24:0] Last Valid Addr CS[2] R/W LBA OE EB D[31:0] Last Valid Data Figure 53. WSC = 3, WEA = 2, WEN = 3, A.WORD/E.HALF Freescale Semiconductor Write Data (V1 Word) Last Valid Data Address V1 Write 1/2 Half Word MC9328MX21S Technical Data, Rev. 1.3 Specifications Address 2/2 Half Word 63 ...

Page 64

... Read haddr V1 hready weim_hrdata Last Valid Data weim_hready BCLK A[24:0] Last Valid Addr CS[2] R/W LBA OE EB (EBC=0) EB (EBC=1) DATA_IN Figure 54. WSC = 3, OEN = 2, A.WORD/E.HALF 64 Address V1 Read 1/2 Half Word MC9328MX21S Technical Data, Rev. 1.3 V1 Word Address 2/2 Half Word Freescale Semiconductor ...

Page 65

... BCLK Last Valid Addr A[24:0] CS[2] R/W LBA OE EB (EBC=0) EB (EBC=1) DATA_IN Figure 55. WSC = 3, OEA = 2, OEN = 2, A.WORD/E.HALF Freescale Semiconductor Last Valid Data Address V1 Read 1/2 Half Word MC9328MX21S Technical Data, Rev. 1.3 Specifications V1 Word Address 2/2 Half Word 65 ...

Page 66

... A[24:0] Last Valid Addr CS[2] R/W LBA OE EB D[31:0] Last Valid Data Figure 56. WSC = 2, WWS = 1, WEA = 1, WEN = 2, A.WORD/E.HALF 66 Write Data (V1 Word) Last Valid Data Address V1 Write 1/2 Half Word MC9328MX21S Technical Data, Rev. 1.3 Unknown Address 2/2 Half Word Freescale Semiconductor ...

Page 67

... A[24:0] Last Valid Addr CS[2] R/W LBA OE EB D[31:0] Last Valid Data Figure 57. WSC = 1, WWS = 2, WEA = 1, WEN = 2, A.WORD/E.HALF Freescale Semiconductor Write Data (V1 Word) Last Valid Data Address V1 Write 1/2 Half Word MC9328MX21S Technical Data, Rev. 1.3 Specifications Unknown Address 2/2 Half Word ...

Page 68

... CS[2] R/W LBA OE EB (EBC=0) EB (EBC=1) DATA_IN D[31:0] Figure 58. WSC = 2, WWS = 2, WEA = 1, WEN = 2, A.HALF/E.HALF 68 Nonseq Write V8 Last Valid Data Address V1 Read Read Data Last Valid Data MC9328MX21S Technical Data, Rev. 1.3 Write Data Read Data Address V8 Write Write Data Freescale Semiconductor ...

Page 69

... BCLK A[24:0] Last Valid Addr CS[2] R/W LBA OE EB (EBC=0) EB (EBC=1) DATA_IN D[31:0] Figure 59. WSC = 2, WWS = 1, WEA = 1, WEN = 2, EDC = 1, A.HALF/E.HALF Freescale Semiconductor Read Idle Nonseq Write V8 Last Valid Data Address V1 Read Read Data Last Valid Data MC9328MX21S Technical Data, Rev. 1.3 ...

Page 70

... Last Valid Addr CS[3:0] R/W LBA OE EB D[31:0] Last Valid Data Figure 60. WSC = 2, CSA = 1, WWS = 1, A.WORD/E.HALF 70 Write Data (Word) Last Valid Data Address V1 Write Write Data (1/2 Half Word) MC9328MX21S Technical Data, Rev. 1.3 Address Write Data (2/2 Half Word) Freescale Semiconductor ...

Page 71

... BCLK A[24:0] Last Valid Addr CS[4] R/W LBA OE EB (EBC=0) EB (EBC=1) DATA_IN D[31:0] Figure 61. WSC = 3, CSA = 1, A.HALF/E.HALF Freescale Semiconductor Nonseq Write V8 Last Valid Data Last Valid Data Address V1 Read Read Data Last Valid Data MC9328MX21S Technical Data, Rev. 1.3 Specifications Write Data ...

Page 72

... BCLK A[24:0] Last Valid Addr CS[4] R/W LBA OE EB (EBC=0) EB (EBC=1) DATA_IN Figure 62. WSC = 2, OEA = 2, CNC = 3, BCM = 1, A.HALF/E.HALF 72 Idle Seq Read V2 Read Data (V1) Address V1 CNC Read Read Data (V1) MC9328MX21S Technical Data, Rev. 1.3 Read Data (V2) Address V2 Read Data (V2) Freescale Semiconductor ...

Page 73

... BCLK A[24:0] Last Valid Addr CS[4] R/W LBA OE EB (EBC=0) EB (EBC=1) DATA_IN D[31:0] Figure 63. WSC = 2, OEA = 2, WEA = 1, WEN = 2, CNC = 3, A.HALF/E.HALF Freescale Semiconductor Idle Nonseq Write V8 Last Valid Data Read Data Address V1 CNC Read Read Data Last Valid Data MC9328MX21S Technical Data, Rev. 1.3 ...

Page 74

... Read haddr V1 hready weim_hrdata weim_hready BCLK A[24:0] Last Valid Addr CS[2] R/W LBA OE EB (EBC=0) EB (EBC=1) ECB DATA_IN Figure 64. WSC = 3, SYNC = 1, A.HALF/E.HALF 74 Nonseq Read V5 Address V1 Read V1 Word V2 Word MC9328MX21S Technical Data, Rev. 1.3 Idle Address V5 V5 Word V6 Word Freescale Semiconductor ...

Page 75

... Last Valid Data weim_hready BCLK A[24:0] Last Valid Addr CS[2] R/W LBA OE EB (EBC=0) EB (EBC=1) ECB DATA_IN Figure 65. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.WORD Freescale Semiconductor Seq Seq Read Read Word V2 Word Address V1 Read V1 Word V2 Word MC9328MX21S Technical Data, Rev. 1.3 Specifications ...

Page 76

... BCLK A[24:0] Last Valid Addr CS[2] R/W LBA OE EB (EBC=0) EB (EBC=1) ECB DATA_IN Figure 66. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.HALF 76 Seq Read V2 V1 Word Address V1 Read V1 1/2 V1 2/2 MC9328MX21S Technical Data, Rev. 1.3 Idle V2 Word Address V2 V2 1/2 V2 2/2 Freescale Semiconductor ...

Page 77

... BCLK Last Valid A[24:0] Addr CS[2] R/W LBA OE EB (EBC=0) EB (EBC=1) ECB DATA_IN Figure 67. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 2, A.WORD/E.HALF Freescale Semiconductor Read Last Valid Data Address V1 Read V1 1/2 MC9328MX21S Technical Data, Rev. 1.3 Specifications Idle Seq V2 V1 Word V2 Word ...

Page 78

... Last Valid A[24:0] Addr CS[2] R/W LBA OE EB (EBC=0) EB (EBC=1) ECB DATA_IN Figure 68. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 1, A.WORD/E.HALF 78 Last Valid Data Address V1 Read V1 1/2 V1 2/2 MC9328MX21S Technical Data, Rev. 1.3 Seq Idle Read V2 V1 Word V2 Word V2 1/2 V2 2/2 Freescale Semiconductor ...

Page 79

... Other bits such as DSZ, OEA, OEN, and so on, may be set according to system and timing requirements of the external device. The waveforms in the following section provide examples of the DTACK signal operation. Freescale Semiconductor Specifications” for more information on how to generate MC9328MX21S Technical Data, Rev. 1.3 ...

Page 80

... DTACK Example Waveforms: Internal ARM AHB Word Accesses to Word-Width (32-bit) Memory HCLK BCLK Last Valid ADDR Addr CS[5] RW LBA OE EB (EBC=0) EB (EBC=1) DTACK DATA_IN Figure 69. DTACK Edge Triggered Read Access, WSC=3F, OEA=8, OEN=5, AGE= Read MC9328MX21S Technical Data, Rev. 1.3 V1 Data Freescale Semiconductor ...

Page 81

... Last Valid Addr CS[0] RW LBA OE EB (EBC=0) EB (EBC=1) DTACK DATA_IN Figure 70. DTACK Level Sensitive Sequential Read Accesses, WSC=2, EW=1, DCT=1, AGE=0 (Example of Freescale Semiconductor Address V1 Read DCT V1 Word DTACK Remaining High) MC9328MX21S Technical Data, Rev. 1.3 Specifications V1+8 V1+4 V1+4 Word ...

Page 82

... Last Valid Addr ADDR CS[0] RWA RW LBA OE EB DTACK DATA_OUT Figure 71. DTACK Level Sensitive Sequential Write Accesses, WSC=2, EW=1, RWA=1, RWN=1, DCT=1, 82 Address V1 RWN Write DCT V1 Word AGE=0 (Example of DTACK Asserting) MC9328MX21S Technical Data, Rev. 1.3 V1+4 V1+8 V1+4 Word V1+8 Freescale Semiconductor ...

Page 83

... SCL Clock Frequency 1 Hold time (repeated) START condition 2 Data hold time 3 Data setup time 4 HIGH period of the SCL clock 5 LOW period of the SCL clock 6 Setup time for STOP condition Freescale Semiconductor Table 39 Bus Timing Parameters 1.8 V ± 0.1 V Minimum Maximum 0 100 114.8 – ...

Page 84

... Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MX21 Product Family 4 Pin Assignment and Package Information ...

Page 85

... MAPBGA Package Dimensions Figure 73 illustrates the MAPBGA 14 mm × × 1.41 mm package, which has 0.65 mm ball pitch. Figure 73. i.MX21 MAPBGA Mechanical Drawing Freescale Semiconductor Pin Assignment and Package Information MC9328MX21S Technical Data, Rev. 1.3 85 ...

Page 86

... Pin Assignment and Package Information 4.2 MAPBGA Package Dimensions Figure 74 illustrates the MAPBGA 17 mm × × 1.45 mm package, which has 0.8 mm spacing between the pads. Figure 74. i.MX21 MAPBGA Mechanical Drawing 86 MC9328MX21S Technical Data, Rev. 1.3 Freescale Semiconductor ...

Page 87

... Table 1 on page 3 Added VM and CVM devices. Table 7 on page 14 Updated Sleep Current values.. Table 40 on page 84 Added Package Drawing for the 17mm x 17mm package. Freescale Semiconductor Table 41. Document Revision History Description of Change MC9328MX21S Technical Data, Rev. 1.3 Document Revision History 87 ...

Page 88

... Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use ...