MCIMX31LCVMN4D Freescale, MCIMX31LCVMN4D Datasheet - Page 58

• Manufacturer Part Number: MCIMX31LCVMN4D
• Manufacturer: Freescale

Specifications of MCIMX31LCVMN4D

• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

3
where CEIL(X) rounds the elements of X to the nearest integers towards infinity.
Electrical Characteristics
4.3.15.3 Interface to Sharp HR-TFT Panels
Figure 49
CLS_RISE_DELAY, CLS_FALL_DELAY, PS_FALL_DELAY, PS_RISE_DELAY,
REV_TOGGLE_DELAY parameters are defined in the SDC_SHARP_CONF_1 and
SDC_SHARP_CONF_2 registers. For other Sharp interface timing characteristics, refer to
Section 4.3.15.2.2, “Interface to Active Matrix TFT LCD Panels, Electrical Characteristics,” on page 55.
The timing images correspond to straight polarity of the Sharp signals.
58
Tdicu
Display interface clock up time
DISPB_D3_DATA
DISPB_D3_SPL
DISPB_D3_CLS
DISPB_D3_REV
=
DISPB_D3_PS
DISPB_D3_CLK
DISPB_D3_HSYNC
1
-- - T
2
depicts the Sharp HR-TFT panel interface timing, and
HSP_CLK
Figure 49. Sharp HR-TFT Panel Interface Timing Diagram—Pixel Level
⋅
ceil
2 DISP3_IF_CLK_UP_WR
--------------------------------------------------------------------- -
⋅
HSP_CLK_PERIOD
SPL pulse width is fixed and aligned to the first data of the line.
Example is drawn with FW+1=320 pixel/line, FH+1=240 lines.
REV toggles every HSYNC period.
IP24
MCIMX31C/MCIMX31LC Technical Data, Rev. 4.3
IP22
Horizontal timing
IP21
IP23
IP25
D1 D2
IP26
1 DISPB_D3_CLK period
Table 46
D320
lists the timing parameters. The
Freescale Semiconductor