PPC405GPR-3DB266 Applied Micro Circuits Corporation, PPC405GPR-3DB266 Datasheet - Page 10

• Manufacturer Part Number: PPC405GPR-3DB266
• Manufacturer: Applied Micro Circuits Corporation

Specifications of PPC405GPR-3DB266

• Family Name: 405GPr
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 266MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.8V
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 456
• Package Type: EBGA
• Lead Free Status / RoHS Status: Not Compliant

405GPr – Power PC 405GPr Embedded Processor
SDRAM Memory Controller
The PPC405GPr Memory Controller core provides a low latency access path to SDRAM memory. A variety of
system memory configurations are supported. The memory controller supports up to four physical banks. Up to
256MB per bank are supported, up to a maximum of 1GB. Memory timings, address and bank sizes, and memory
addressing modes are programmable.
Features include:
External Peripheral Bus Controller (EBC)
10
• Supports PCI target access to all PLB address spaces
• Supports PowerPC processor boot from PCI memory
• 11x8 to 13x11 addressing for SDRAM (2- and 4-bank)
• 32-bit memory interface support
• Programmable address compare for each bank of memory
• Industry standard 168-pin DIMMS are supported (some configurations)
• PC-133 support for 133 MHz memory
• 4MB to 256MB per bank
• Programmable address mapping and timing
• Auto refresh
• Page mode accesses with up to 4 open pages
• Power management (self-refresh)
• Error checking and correction (ECC) support
• Supports eight banks of ROM, EPROM, SRAM, Flash memory, or slave peripherals
• Up to 66MHz operation
• Burst and non-burst devices
• 8-, 16-, 32-bit byte-addressable data bus width support
• Latch data on Ready
• Programmable 2K clock time-out counter with disable for Ready
• Programmable access timing per device
- Standard single-error correct, double-error detect coverage
- Aligned nibble error detect
- Address error logging
- 0–255 wait states for non-bursting devices
- 0–31 burst wait states for first access and up to 7 wait states for subsequent accesses
Revision 2.05 – March 24, 2008
Data Sheet
AMCC