MC9S12DG128CFUE Freescale, MC9S12DG128CFUE Datasheet - Page 62

• Manufacturer Part Number: MC9S12DG128CFUE
• Manufacturer: Freescale

Specifications of MC9S12DG128CFUE

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 50MHz
• Interface Type: SCI/SPI/I2C/CAN
• Total Internal Ram Size: 8KB
• # I/os (max): 91
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.25V
• Operating Supply Voltage (min): 2.25/2.35/4.5V
• On-chip Adc: 2(8-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 128KB
• Lead Free Status / RoHS Status: Compliant

Function 1
Device User Guide — 9S12DT128DGV2/D V02.16
Pin Name
PK[5:0]
PJ[1:0]
62
PM7
PM6
PM5
PM4
PM3
PM2
PH6
PH5
PH4
PH3
PH2
PH1
PH0
PK7
PJ7
PJ6
Function 2
XADDR[19:
Pin Name
BF_PSLM
BF_PERR
BF_PROK
BF_PSYN
KWJ[1:0]
RX_BF
TX_BF
KWH6
KWH5
KWH4
KWH3
KWH2
KWH1
KWH0
KWJ7
KWJ6
ECS
14]
Function 3
Pin Name
ROMCTL
RXCAN4
TXCAN4
RXCAN4
RXCAN0
RXCAN1
TXCAN4
TXCAN0
TXCAN1
MOSI1
MISO1
SCK1
SS1
---
---
---
—
—
Function 4
Pin Name
RXCAN4
RXCAN0
TXCAN4
TXCAN0
SCL
SDA
—
—
—
—
—
—
—
—
—
—
—
—
Function 5
Pin Name
RXCAN0
TXCAN0
MOSI0
MISO0
SCK0
SS0
—
—
—
—
—
—
—
—
—
—
—
—
Powered
VDDR
VDDR
VDDR
VDDR
VDDR
VDDR
VDDR
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
by
PUPKE
PUPKE
PUCR/
PUCR/
PERM/
PERM/
PERM/
PERM/
PERM/
PERM/
PERH/
PERH/
PERH/
PERH/
PERH/
PERH/
PERH/
PERJ/
PPSH
PPSH
PPSH
PPSH
PPSH
PPSH
PPSH
PERJ/
PERJ/
PPSM
PPSM
PPSM
PPSM
PPSM
PPSM
CTRL
PPSJ
PPSJ
PPSJ
Internal Pull
Resistor
Disabled Port H I/O, Interrupt
Disabled Port H I/O, Interrupt
Disabled Port H I/O, Interrupt
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Reset
Freescale Semiconductor
State
Up
Up
Up
Up
Up
Port H I/O, Interrupt,
SS of SPI1
Port H I/O, Interrupt,
SCK of SPI1
Port H I/O, Interrupt,
MOSI of SPI1
Port H I/O, Interrupt,
MISO of SPI1
Port J I/O, Interrupt,
TX of CAN4, SCL of
IIC
Port J I/O, Interrupt,
RX of CAN4, SDA of
IIC
Port J I/O, Interrupts
Port K I/O,
Emulation Chip
Select, ROM Control
Port K I/O, Extended
Addresses
Port M I/O, BF slot
mismatch pulse, TX
of CAN4
Port M I/O, BF illegal
pulse/message
format error pulse,
RX of CAN4
Port M I/O, BF
reception ok pulse,
TX of CAN0, CAN4,
SCK of SPI0
Port M I/O, BF sync
pulse (Rx/Tx) OK
pulse o/p, RX of
CAN0, CAN4, MOSI
of SPI0
Port M I/O, TX of BF,
CAN1, CAN0, SS of
SPI0
Port M I/O, RX of BF,
CAN1, CAN0, MISO
of SPI0
Description