MC9S08QG8CPBE Freescale, MC9S08QG8CPBE Datasheet - Page 77
MC9S08QG8CPBE
Manufacturer Part Number
MC9S08QG8CPBE
Description
Manufacturer
Freescale
Datasheet
1.MC9S08QG8CPBE.pdf
(314 pages)
Specifications of MC9S08QG8CPBE
Cpu Family
HCS08
Device Core Size
8b
Frequency (max)
20MHz
Interface Type
I2C/SCI/SPI
Total Internal Ram Size
512Byte
# I/os (max)
12
Number Of Timers - General Purpose
1
Operating Supply Voltage (typ)
2.5/3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
1.8V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Through Hole
Pin Count
16
Package Type
PDIP
Program Memory Type
Flash
Program Memory Size
8KB
Lead Free Status / RoHS Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S08QG8CPBE
Manufacturer:
CYPRESS
Quantity:
310
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1
5.8.9
This high page register contains status and control bits to configure the stop mode behavior of the MCU.
See
Freescale Semiconductor
This bit can be written only one time after reset. Additional writes are ignored.
Reset:
PPDACK
PPDC
PPDF
Field
PDC
PDF
Section 3.6, “Stop
4
3
2
1
0
W
R
System Power Management Status and Control 2 Register
(SPMSC2)
Figure 5-11. System Power Management Status and Control 2 Register (SPMSC2)
Power Down Flag — This read-only status bit indicates the MCU has recovered from stop1 mode.
0 MCU has not recovered from stop1 mode.
1 MCU recovered from stop1 mode.
Partial Power Down Flag — This read-only status bit indicates that the MCU has recovered from stop2 mode.
0 MCU has not recovered from stop2 mode.
1 MCU recovered from stop2 mode.
Partial Power Down Acknowledge — Writing a 1 to PPDACK clears the PPDF and the PDF bits.
Power Down Control — The PDC bit controls entry into the power down (stop2 and stop1) modes.
0 Power down modes are disabled.
1 Power down modes are enabled.
Partial Power Down Control — The PPDC bit controls which power down mode is selected.
0 Stop1 full power down mode enabled if PDC set.
1 Stop2 partial power down mode enabled if PDC set.
0
0
7
= Unimplemented or Reserved
Modes,” for more information on stop modes.
0
0
6
Table 5-13. SPMSC2 Register Field Descriptions
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5
0
0
5
PDF
0
4
Description
Chapter 5 Resets, Interrupts, and General System Control
PPDF
3
0
PPDACK
0
0
2
PDC
0
1
1
PPDC
0
0
1
75
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