STPCE1HEBIE STMicroelectronics, STPCE1HEBIE Datasheet - Page 75
STPCE1HEBIE
Manufacturer Part Number
STPCE1HEBIE
Description
Manufacturer
STMicroelectronics
Datasheet
1.STPCE1HEBIE.pdf
(87 pages)
Specifications of STPCE1HEBIE
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Processing Unit
Microprocessor
Operating Supply Voltage (min)
2.45/3V
Operating Supply Voltage (typ)
2.5/3.3V
Operating Supply Voltage (max)
2.7/3.6V
Package Type
BGA
Screening Level
Industrial
Pin Count
388
Mounting
Surface Mount
Rad Hardened
No
Lead Free Status / RoHS Status
Compliant
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6.4.3. PCI INTERFACE
6.4.3.1. Introduction
In order to achieve a PCI interface which work at
clock
consideration has to be given to the timing of the
interface with all the various electrical and
physical constraints taken into consideration.
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
frequencies
up
Bridge
South
Bridge
North
Strap Options
delay
clock
to
HCLK PLL
Deskewer
MD[30:27]
33MHz,
MD[7:6]
Figure 6-21. Clock Scheme
Release 1.3 - January 29, 2002
1/2
1/3
1/4
careful
MD[17,4]
MUX
STPC
6.4.3.2. PCI Clocking Scheme
The PCI Clocking Scheme deserves a special
mention here. Basically the PCI clock (PCICLKO)
is generated on-chip from HCLK through a
programmable delay line and a clock divider. The
nominal frequency is 33MHz. This clock must be
looped to PCICLKI and goes to the internal South
Bridge through a deskewer. On the contrary, the
internal North Bridge is clocked by HCLK, putting
some additionnal constraints on T
PCICLKI
PCICLKO
HCLK
AD[31:0]
DESIGN GUIDELINES
0
T
T
and T
0
1
1
.
T
2
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