MCZ33991EG Freescale, MCZ33991EG Datasheet - Page 10

• Manufacturer Part Number: MCZ33991EG
• Manufacturer: Freescale

Specifications of MCZ33991EG

• Operating Current: 6mA
• Operating Temperature Classification: Automotive
• Package Type: SOIC W
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Lead Free Status / RoHS Status: Compliant

Table 3. Static Electrical Characteristics (continued)
10
33991
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
SPI TIMING INTERFACE
Notes
specified in the environmental requirements section. Digital Interface timing is based on a symmetrical 50% duty cycle SCLK
Clock Period of 333 ns. The device shall be fully functional for slower clock speeds.
Recommended Frequency of SPI Operation
Falling edge of CS to Rising Edge of SCLK (Required Setup Time)
Falling edge of SCLK to Rising Edge of CS (Required Setup Time)
SI to Falling Edge of SCLK (Required Setup Time)
Falling Edge of SCLK to SI (Required Hold Time)
SO Rise Time (CL=200pF)
SO Fall Time (CL=200pF)
SI, CS, SCLK, Incoming Signal Rise Time
SI, CS, SCLK, Incoming Signal Fall Time
Falling Edge of RST to Rising Edge of RST (Required Setup Time)
Rising Edge of RST to Falling Edge of CS (Required Setup Time)
Time from Falling Edge of CS to SO Low Impedance
Time from Rising Edge of CS to SO High Impedance
Time from Rising Edge of SCLK to SO Data Valid
0.2 V
14.
15.
16.
17.
18.
19.
20.
(Characteristics noted under conditions 4.75 V < V
The device shall meet all SPI interface-timing requirements specified in the SPI Interface Timing, over the temperature range
DD
Rising Edge of CS to Falling Edge of CS (Required Setup
Time)
The maximum setup time that is specified for the 33991 is the minimum time needed from the micro controller to guarantee correct
operation.
Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
Time required for output status data to be available for use at SO. 1 K Ohm load on SO
Time required for output status data to be terminated at SO. 1 K Ohm load on SO.
Time required to obtain valid data out from SO following the rise of SCLK.
This value is for a 1 MHz calibrated internal clock; it will change proportionally as the internal clock frequency changes.
< = SO> = 0.8 V
(15) (20)
DD
Characteristic
, CL = 200 pF
(16)
(16)
(15)
(19)
(15)
(17)
(18)
DD
< 5.25 V, -40°C < T
(15)
(15)
(15)
(15)
TSI
T
Symbol
T
T
TS
Tw
T
SO(DIS)
T
SO(EN)
Tr
Tf
T
VALID
Tr
Tf
T
f
LEAD
(HOLD)
SPI
LAG
EN
LSU
SO
SO
RST
CS
SI
SI
J
< 150°C, unless otherwise noted)
Min
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Analog Integrated Circuit Device Data
Typ
1.0
1.3
50
50
25
25
25
25
65
—
—
—
—
—
—
Freescale Semiconductor
Max
167
167
145
105
3.0
3.0
5.0
5.0
4.0
83
83
50
50
50
50
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
ns
µs
ns