IRMCF371 International Rectifier, IRMCF371 Datasheet
IRMCF371
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IRMCF371 Summary of contents
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... CMOS Description IRMCF371 is a high performance RAM based motion control IC designed primarily for appliance applications. IRMCF371 is designed to achieve low cost and high performance control solutions for advanced inverterized appliance motor control. IRMCF371 contains two computation engines. One is Motion Control Engine (MCE magnet motors ...
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... Overview ....................................................................................................................................4 2 IRMCF371 Block Diagram and Main Functions.........................................................................5 3 Pinout.........................................................................................................................................7 4 Input/Output of IRMCF371.........................................................................................................8 4.1 8051 Peripheral Interface Group .........................................................................................8 4.2 Motion Peripheral Interface Group ......................................................................................9 4.3 Analog Interface Group .......................................................................................................9 4.4 Power Interface Group ......................................................................................................10 4.5 Test Interface Group .........................................................................................................10 5 Application Connections .......................................................................................................... Characteristics ...................................................................................................................12 6.1 Absolute Maximum Ratings...............................................................................................12 6 ...
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... Figure 1. Typical Application Block Diagram Using IRMCF371.....................................................4 Figure 2. IRMCF371 Internal Block Diagram .................................................................................5 Figure 3. IRMCF371 Pin Configuration..........................................................................................7 Figure 4. Input/Output of IRMCF371..............................................................................................8 Figure 5. Application Connection of IRMCF371 ..........................................................................11 Figure 6. Clock Frequency vs. Power Consumption....................................................................12 Table 1. Absolute Maximum Ratings ...........................................................................................12 Table 2. System Clock Frequency ...............................................................................................12 Table 3. Digital I/O DC Characteristics ........................................................................................13 Table 4. PLL DC Characteristics .................................................................................................14 Table 5 ...
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... IRMCF371 is intended for development purpose and contains 48K bytes of RAM, which can be loaded from external EEPROM for 8051 program execution. For high volume production, IRMCK371 contains OTP ROM in place of program RAM to reduce the cost. Both IRMCF371 and IRMCK371 come in the same 48-pin QFP package with identical pin configuration to facilitate PC board layout and transition to mass production Figure 1 ...
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... IRMCF371 Block Diagram and Main Functions IRMCF371 block diagram is shown in Figure 2. Figure 2. IRMCF371 Internal Block Diagram IRMCF371 contains the following functions for sensorless AC motor control applications: • Motion Control Engine (MCE o Proportional plus Integral block o Low pass filter o Differentiator and lag (high pass filter) ...
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... One channel of analog output (8-bit PWM) o UART C/SPI port o 48K byte program RAM loaded from external EEPROM o 2K byte data RAM. Note 1: Total size of RAM is 8K byte including MCE program, MCE data, and 8051 data. Different sizes can be allocated depending on applications. Note 1 Note 1 IRMCF371 6 ...
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... Pinout 48 XTAL0 1 XTAL1 2 P1.0/T2 3 P1.1/RXD 4 P1.2/TXD 5 P1.3/SYNC/SCK 6 P1.4/CAP 7 VDD2 8 VSS 9 VDD1 10 P2.0/NMI 11 P2 Figure 3. IRMCF371 Pin Configuration (Top View IRMCF371 P3.0/INT2/CS1 35 PWMUH 34 PWMUL 33 PWMVH PWMVL 32 PWMWH 31 PWMWL 30 GATEKILL 29 VDD1 28 VSS 27 VDD2 26 AIN2 25 7 ...
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... Input/Output of IRMCF371 All I/O signals of IRMCF371 are shown in Figure 4. All I/O pins are 3.3V logic interface except A/D interface pins. XTAL0 Crystal XTAL1 UART P1.2/TXD Interface P1.1/RXD I2C SDA/CS0 Interface SCL/SO-SI P1.0/T2 P1.3/SYNC/SCK P1.4/CAP Discrete I/O P2.0/NMI P2.1 P3.0/INT2/CS1 P3.2/INT0 System Reset RESET P5 ...
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... Input, Operational amplifier positive input for shunt resistor current sensing IFB- Input, Operational amplifier negative input for shunt resistor current sensing IFBO Output, Operational amplifier output for shunt resistor current sensing 2 C clock output or SPI data 2 C Data line or SPI chip select EEPROM IRMCF371 9 ...
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... Test Interface Group TSTMOD Must be tied to VSS, used only for factory testing. P5.1/TSM Input/output port 5.1, configured as JTAG port by default P5.2/TDO Input/output port 5.2, configured as JTAG port by default P5.3/TDI Input/output port 5.3, configured as JTAG port by default TCK Input, JTAG test clock IRMCF371 10 ...
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... Application Connections Typical application connection is shown in Figure 5. All components necessary to implement a complete sensorless drive control algorithm are shown connected to IRMCF371. Figure 5. Application Connection of IRMCF371 IRMCF371 11 ...
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... -40 ˚C - -65 ˚C - Min Typ 32 - Table 2. System Clock Frequency 100 Clock Frequency (MHz) IRMCF371 Max Condition 3.6 V Respect to VSS 1.98 V Respect to VSS 1.98 V Respect to AVSS 3.65 V Respect to VSS 85 ˚C 150 ˚C Max Unit 128 MHz VDD2 (1.8V) VDD1 (3.3V) Total ...
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... PWMUL, PWMUH, PWMVL, PWMVH, PWMWL, PWMWH pins. Min Typ Max 3.0 V 3.3 V 3.6 V 1.62 V 1.8 V 1. 0.8 V 2 3.6 pF ±10 nA ±1 μA 8.9 mA 13.2 mA 15.2 mA 12 17.9 mA 26.3 mA 33.4 mA 24 IRMCF371 Condition Recommended Recommended Recommended Recommended ( (1) 13 ...
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... Data guaranteed by design. Min Typ 1. PLLVSS 0.8* V PLLVDD Table 4. PLL DC Characteristics Min Typ 1. ( kΩ 100 μA IRMCF371 Condition Max 1.92 V Recommended 0. 1.8 V PLLVDD (1) V PLLVDD 1.8 V PLLVDD PLLVDD (1) Condition Max 1.89 V Recommended 1.8 V AVDD 1.2 V Recommended 1 1.8 V AVDD (1) - Requested 20 kΩ ...
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... Ratio Table 7. CMEXT and AREF DC Characteristics Note: (1) Data guaranteed by design. Min Typ 1.53 V 1.66 V 1. Table 6. UVcc DC Characteristics Min Typ 495 mV 600 mV 495 mV 600 mV -0. IRMCF371 Condition Max 1. 3.3 V DD1 1. 3.3 V DD1 - Condition Max 700 1.8 V AVDD 700 1.8 V AVDD (1) - ...
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... PLL lock time LOCK Note: (1) Data guaranteed by design Min Typ 3.2 MHz 4 MHz 32 MHz 50 MHz F ÷ 256 - CLKIN - 200 psec - Table 8. PLL AC Characteristics R =1M 1 =10 Xtal =30PF C =30PF 2 IRMCF371 Max Condition (1) 60 MHz (see figure below) (1) 128 MHz (1) - (1) - (1) - (1) 500 μsec 16 ...
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... Table 10. Current Sensing OP amp Amp AC Characteristics Note: (1) Data guaranteed by design. Min Typ - - 2.05 μsec - - S/H Voltage t SAMPLE T HOLD Min Typ - 10 V/μsec Ω - 400 ns IRMCF371 Max Condition (1) 10 μsec Voltage droop ≤ 15 LSB (see figure below) Max Condition - AVDD ( ( 1 AVDD ( ...
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... SYNC to PWM output dSYNC3 delay time Table 11. SYNC AC Characteristics Note: (1) AIN1 through AIN6 channels are converted once every 6 SYNC events t wSYNC t dSYNC1 t dSYNC2 t dSYNC3 Min Typ - IRMCF371 Max Unit - SYSCLK 100 SYSCLK 200 SYSCLK (1) 2 SYSCLK 18 ...
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... GATEKILL to SVPWM AC Timing Unless specified 25˚C. Symbol Parameter t GATEKILL pulse width wGK t GATEKILL to PWM dGK output delay Table 12. GATEKILL to SVPWM AC Timing Min Typ Max 100 IRMCF371 Unit SYSCLK SYSCLK 19 ...
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... Interrupt AC Timing Unless specified 25˚C. Symbol Parameter t INT0, INT1 Interrupt wINT Assertion Time t INT0, INT1 latency dINT Min Typ Table 13. Interrupt AC Timing IRMCF371 Max Unit - SYSCLK 4 SYSCLK 20 ...
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... Note read setup time is determined by the programmable filter time applied to I communication I2CLK I2CLK I2WSETUP I2WHOLD I2RSETUP Min Typ 10 0.25 0.25 0.25 0. filter time 1 2 Table 14 Timing IRMCF371 t I2EN1 t I2RHOLD t I2EN2 Max Unit - 8192 SYSCLK - - T I2CLK - - T I2CLK - - T I2CLK - - T I2CLK - - SYSCLK ...
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... CS to data delay time CSDELAY t CLK falling edge to data WRDELAY delay time t CS high time between two CSHIGH consecutive byte transfer t CS hold time CSHOLD Min Typ 1 Table 15. SPI Write AC Timing IRMCF371 Max Unit - SYSCLK - T SPICLK - T SPICLK 10 nsec 10 nsec - T SPICLK - T SPICLK 22 ...
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... SPI read data setup time RDSU t SPI read data hold time RDHOLD t CS high time between two CSHIGH consecutive byte transfer t CS hold time CSHOLD Min Typ 1 Table 16. SPI Read AC Timing IRMCF371 Max Unit - SYSCLK - T SPICLK - T SPICLK 10 nsec - nsec - nsec - T SPICLK - T SPICLK 23 ...
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... Each bit including start and stop bit is sampled three times at center of a bit at an interval of 1/ three sampled values do not agree, then UART noise error is generated. BAUD Data and Parity Bit Stop Bit T UARTFIL Min Typ - 57600 - 1/16 Table 17. UART AC Timing IRMCF371 Max Unit - bit/sec - T BAUD 24 ...
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... CAPTURE input low CAPLOW time t CAPTURE falling edge CRDELAY to capture register latch time t CAPTURE rising edge CLDELAY to capture register latch time t CAPTURE input INTDELAY interrupt latency time Min Typ Table 18. CAPTURE AC Timing IRMCF371 Max Unit - SYSCLK - SYSCLK - SYSCLK 4 SYSCLK 4 SYSCLK 4 SYSCLK 25 ...
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... Unless specified 25˚C. Symbol Parameter T TCK Period JCLK t TCK High Period JHIGH t TCK Low Period JLOW t TCK to TDO propagation CO delay time t TDI/TMS setup time JSETUP t TDI/TMS hold time JHOLD Min Typ - - Table 19. JTAG AC Timing IRMCF371 Max Unit 50 MHz - nsec - nsec 5 nsec - nsec - nsec 26 ...
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... PWM gate drive for phase W low side, configurable up O PWM gate drive for phase W high side, configurable up O PWM gate drive for phase V low side, configurable up IRMCF371 Description Crystal input Crystal output 2 to boot from I C EEPROM 1.8V digital power Digital common 3 ...
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... I Test mode input, must be tied to VSS down I/O Reset, low true, Schmitt trigger input P P Table 20. Pin List IRMCF371 Description either high or low true either high or low true either high or low true input or SPI chip select 1 input Digital common I2C clock or SPI data ...
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... Package Dimensions IRMCF371 29 . ...
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... IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 252-7105 www.irf.com IRMCF371 YWWP XXXXXX Order Information This product has been designed and qualified for the industrial level Qualification standards can be found at Data and specifications subject to change without notice. 12/05/2006 IRMCF371 IR Logo Production Lot The LQFP-48 is MSL3 qualified www.irf.com <http://www.irf.com> 30 ...