LSISAS1068E LSI, LSISAS1068E Datasheet - Page 10

• Manufacturer Part Number: LSISAS1068E
• Manufacturer: LSI

Specifications of LSISAS1068E

• Lead Free Status / RoHS Status: Not Compliant

DMA Arbiter
PCI Timer and Configuration
SIO A and SIO B
External Memory
I
10 of 30
DB08-000274-03
2
C
The LSISAS1068E provides the ability to transfer system memory blocks
to and from local memory through the descriptor-based DMA arbiter and
router. The DMA channel includes a system DMA FIFO and the internal
bus interface logic.
This PCI timer and configuration module supports the PCI configuration
register space and a power-on reset (POR).
The LSISAS1068E provides two SGPIO interfaces that are compliant
with the SFF-8485 specification. A typical use of the serial I/O (SIO)
modules is to control LEDs. The SIO A signals are associated with
Quad Port Module 0. The SIO B signals are associated with Quad Port
Module 1. The SIO modules are SFF-8485 compliant.
The external memory controller block provides an interface for flash ROM,
NVSRAM, and PBSRAM devices. The external memory bus provides a
32-bit memory bus, parity checking, and chip select signals for PBSRAM,
NVSRAM, and flash ROM. The flash ROM and NVSRAM are capable of
8-bit accesses, while the PBSRAM is capable of 32-bit accesses.
Most configurations use a flash ROM to store firmware, configuration
information, and persistent data information. The LSISAS1068E uses a
PBSRAM to support super large drive count (SLDC) applications, or to
support firmware download boot procedures. In SLDC applications, each
LSISAS1068E controller can support up to 1023 drives.
The LSISAS1068E contains an Inter-IC (I
with peripherals. The I
the bus and sustains data rates up to 400 Kbits/s. The I
accomplishes byte-wise bidirectional data transfers by using either an
interrupt or a polling handshake at the completion of each byte. The I
block controls all bus timing and performs bus-specific sequences.
LSISAS1068E PCI Express to 8-Port Serial Attached SCSI Controller
October 2006 - Version 2.1
Copyright © 2004–2006 by LSI Logic Corporation. All rights reserved.
2
C block operates as either a master or a slave on
2
C) block that communicates
2
C block
2
C