AM53CF96KC/W AMD (ADVANCED MICRO DEVICES), AM53CF96KC/W Datasheet - Page 30

• Manufacturer Part Number: AM53CF96KC/W
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM53CF96KC/W

• Lead Free Status / RoHS Status: Not Compliant

the PERE bit is reset and bad parity occurs it is not de-
tected and no action is taken.
CNTLREG1 – Bit 3 – STE – Self Test Enable
The STE bit is for test use only. When the STE bit is set
the device is placed in a test mode which enables the
device to access the test register at address 0AH. To re-
set this bit and to resume normal operation the device
must be issued a hard or soft reset.
Clock Factor Register (09H) Write
The Clock Factor Register (CLKFREG) must be set to
indicate the input frequency range of the device. This
value is crucial for controlling various timings to meet the
SCSI specification. The value of bits CLKF 2:0 can be
calculated by rounding off the quotient of (Input Clock
Frequency in MHz)/(5 MHz). The device has a fre-
quency range of 10 to 40 MHz.
CLKFREG – Bits 7:3 – RES – Reserved
CLKFREG – Bits 2:0 – CLKF 2:0 – Clock Factor 2:0
The CLKF 2:0 bits specify the binary coded value of the
clock factor. The CLKF 2:0 bits will default to a value of 2
by a hard or soft reset.
30
AMD
Clock Factor Register
CLKFREG
RES
7
x
RES
6
x
RES
5
x
RES
4
Am53CF94/Am53CF96
x
RES
3
x
CLKF2
2
0
CNTLREG1 – Bit 2:0 – CID 2:0 – Chip ID 2:0
The Chip ID 2:0 bits specify the binary coded value of
the device ID on the SCSI bus. The device will arbitrate
with this ID and will respond to Selection or Reselection
to this ID. At power-up the state of these bit are unde-
fined. These bits are not affected by hard or soft reset.
CLKF2
CLKF1
1
1
Address: 09
0
0
1
1
1
1
0
Type: Write
CLKF0
0
0
CLKF1
H
Clock Factor 2:0
Reserved
Reserved
Reserved
Reserved
Reserved
1
1
0
0
1
1
0
CLKF0 Frequency in MHz
0
1
0
1
0
1
0
17348B-29
Input Clock
10.01 to 15
15.01 to 20
20.01 to 25
25.01 to 30
30.01 to 35
35.01 to 40
10