LSISAS1064E LSI, LSISAS1064E Datasheet - Page 14

• Manufacturer Part Number: LSISAS1064E
• Manufacturer: LSI

Specifications of LSISAS1064E

• Lead Free Status / RoHS Status: Not Compliant

Memory Interface Signals
14 of 30
DB08-000275-03
UART_TX
This section describes the memory interface signals.
MCLK
ADSC/
ADV/
MAD[31:0]
MADP[3:0]
MOE[1:0]/
MWE[1:0]/
BWE[3:0]/
LSISAS1064E PCI Express to 4-Port Serial Attached SCSI Controller
May 2006 - Version 2.0
UART Transmit
This signal provides the UART transmit signal.
Memory Clock
All synchronous RAM control/data signals reference the
rising edge of this clock.
Address-Strobe-Controller
Asserting this active LOW signal initiates read, write, or
chip deselect cycles.
Advance
Asserting this active LOW signal increments the burst
address counter of the selected synchronous SRAM.
Multiplexed Address/Data
These signals provide the address and data bus for the
flash ROM and NVSRAM. These signals also provide
Power-On Sense configuration functions to the
LSISAS1064E. These signals are internally pulled LOW.
Memory Parity
These signals provide parity checking for MAD[31:0].
These signals are internally pulled HIGH.
Memory Output Enables
Asserting these active LOW signals enable the selected
flash ROM or NVSRAM device to drive data. MOE1/
enables flash ROM devices. MOE0/ enables NVSRAM
devices.
Memory Write Enables
The MWE[1:0]/ signals provide memory enable signals.
Memory Byte Write Enables
BWE[3]/ and BWE[2]/ enable partial word writes to the
flash ROM and the NVSRAM if FLASH_CS/ or
NVSRAM_CS/ is asserted.
Copyright © 2004–2006 by LSI Logic Corporation. All rights reserved.
Input/Output
Input/Output
Output
Output
Output
Output
Output
Output
Output