LSI53C101066 LSI, LSI53C101066 Datasheet - Page 3

• Manufacturer Part Number: LSI53C101066
• Manufacturer: LSI

Specifications of LSI53C101066

• Lead Free Status / RoHS Status: Not Compliant

S C S I P r o c e s s o r s
a single chip. Each controller supports wide Ultra160 SCSI synchronous transfer
rates up to 160 MBps on a LVD SCSI bus. Integrated LVDlink
support both LVD and single-ended signals with no external transceivers
required. Fast SCSI, Ultra SCSI, Ultra2 SCSI, and Ultra160 SCSI are all
supported by the LSI53C1010.
transfer rates with an input frequency of 40 MHz. The 8 KB of internal RAM per
channel for SCRIPTS
reducing the time spent on the PCI bus. A 944-byte DMA FIFO on each channel
allows the device to efficiently burst up to 512 bytes across the PCI bus. SCSI
bus phase mismatches are handled in SCRIPTS, reducing CPU utilization.
Figure 2. LSI53C1010 functional signal grouping
The LSI53C1010 provides two independent Ultra160 SCSI controllers on
An on-chip SCSI clock quadrupler allows the chip to achieve Ultra160 SCSI
™
instruction storage allow all accesses to remain internal,
CLK
RST/
REQ/
GNT/
REQ64/
ACK64/
AD[63:0]
C_BE[7:0]/
IDSEL
FRAME/
IRDY/
TRDY/
DEVSEL/
STOP/
PERR/
SERR/
PAR
PAR64
INTA/
INTB/
ALT_INTA/
ALT_INTB/
INT_DIR
M66EN
ENABLE66
A_GPIO0_FETCH/
A_GPIO1_MASTER/
A_GPIO2
A_GPIO3
A_GPIO4
B_GPIO0_FETCH/
B_GPIO1_MASTER/
B_GPIO2
B_GPIO3
B_GPIO4
MWE/
MCE/
MOE/_TESTOUT
MAS0/
MAS1/
MAD7-0
SCSI Function A GPIO
SCSI Function B GPIO
Memory Interface
64-bit, 66 MHz PCI
LSI53C1010
329 PBGA
SCSI Function A
SCSI Function B
Test Interface
MOE/_TESTOUT
SCAN_MODE
A_DIFFSENS
B_DIFFSENS
TEST_RSTN
A_SD[15:0]/
A_SDP[1:0]/
B_SD[15:0]/
B_SDP[1:0]/
TEST_HSC
A_SREQ2/
B_SREQ2/
A_SACK2/
B_SACK2/
A_SMSG/
B_SMSG/
TEST_PD
A_SREQ/
B_SREQ/
A_SACK/
B_SACK/
A_SC_D/
A_SBSY/
A_SATN/
A_SRST/
B_SC_D/
B_SBSY/
B_SATN/
B_SRST/
A_SSEL/
B_SSEL/
A_SI_O/
B_SI_O/
RBIAS
SCLK
TMS
TDO
TCK
TDI
™
transceivers
K E Y F E A T U R E S ( C o n t i n u e d )
• Proven integrated LVDlink
• Comprehensive SureLINK
• IEEE 1149.1 JTAG boundary scan
• Flash and local memory interface
• Packaged in a 329 PBGA
• Supported in Storage Device
transceivers for direct attach to
either Low Voltage Differential
(LVD) or single-ended (SE)
SCSI buses
domain validation
• Basic (Level 1) with
• Enhanced (Level 2) with
• Margined (Level 3) with
Management System (SDMS
software release 4.6
• Full operating system support:
• Server Management Cl
inquiry command
read/write buffer
margining of LVD drive
strength and programmable
skew test
- Windows
- Linux
- Solaris
- UnixWare
- Novell
- OS/2
(component instrumentation)
95/98 and 2000
™
®
™
NetWare
®
™
NT
®
4.0,
®
™
)
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