ISP1582BSUM STEricsson, ISP1582BSUM Datasheet - Page 48

• Manufacturer Part Number: ISP1582BSUM
• Manufacturer: STEricsson

Specifications of ISP1582BSUM

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / RoHS Status: Compliant

Table 71.
ISP1582_9
Product data sheet
Bit
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Test Mode register: bit allocation
8.5.6 Test Mode register (address: 84h)
FORCEHS
unchanged
W
7
R/W
7
0
Table 70.
When bit PWRON in the Mode register is logic 1, the chip is powered. In such a case, you
do not need to issue the Unlock command because the microprocessor is powered and
therefore, the RD_N, WR_N and CS_N signals maintain their states.
When bit PWRON is logic 0, the RD_N, WR_N and CS_N signals are floating because the
microprocessor is not powered. To protect the ISP1582 registers from being corrupted
during suspend, register write is locked when the chip goes into suspend. Therefore, you
need to issue the Unlock command to unlock the ISP1582 registers.
This 1-byte register allows the firmware to set pins DP and DM to predetermined states for
testing purposes. The bit allocation is given in
Remark: Only one bit can be set to logic 1 at a time. This must be implemented for the
Hi-Speed USB logo compliance testing. To exit test mode, power cycle is required.
Table 72.
[1]
[2]
Bit
15 to 0
Bit
7
6 to 5
4
3
2
1
0
Either FORCEHS or FORCEFS must be set at a time.
Of the four bits (PRBS, KSTATE, JSTATE and SE0_NAK), only one bit must be set at a time.
W
6
Symbol
FORCEHS
-
FORCEFS
PRBS
KSTATE
JSTATE
SE0_NAK
6
-
-
-
Unlock Device register: bit description
Test Mode register: bit description
reserved
Symbol
ULCODE[15:0]
W
5
Rev. 09 — 29 September 2009
Description
Force High-Speed: Logic 1
and disables the chirp detection logic.
reserved
Force Full-Speed: Logic 1
only and disables the chirp detection logic.
Predetermined Random Pattern: Logic 1
in a predetermined random pattern.
K-State: Logic 1
J-State: Logic 1
SE0 NAK: Logic 1
The device only responds to a valid high-speed IN token with a NAK.
5
-
-
-
Description
Unlock Code: Writing data AA37h unlocks the internal registers
and FIFOs for writing, following a resume.
unchanged
FORCEFS
W
R/W
4
not applicable
not applicable
4
0
[2]
[2]
[2]
sets pins DP and DM to the J state.
sets pins DP and DM to the K state.
sets pins DP and DM to a high-speed quiescent state.
PRBS
W
R/W
3
[1]
[1]
3
0
0
Table
forces the physical layer to full-speed mode
forces the hardware to high-speed mode only
Hi-Speed USB peripheral controller
71.
KSTATE
R/W
W
2
2
0
0
[2]
sets pins DP and DM to toggle
JSTATE
© ST-ERICSSON 2009. All rights reserved.
R/W
W
1
1
0
0
ISP1582
SE0_NAK
R/W
W
0
0
0
0
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